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blynskey_thinci
Observer
Observer
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Registered: ‎07-25-2018

Zynq UltraScale+ LPDDR4 signal skew

Hi,

In UG583 (v1.17), table 2-45, the CK to DQS skew-constraint is given as a single value: 500ps. For other types of DDR, this skew constraint is given as a range of acceptable values.

Could you explain please - is this a mistake? It seems wrong to tune our trace-delays to hit one specific large delay such as this.

The PS LPDDR4 PHY can run a up to 2400Mbs, at which frequency a skew of 500ps is greater than a bit-cell in duration. This is confusing, and so I need some clarification.

   What CK to DQS skew is needed for PS LPDDR4?

 

Best regards,

 

 - Brendan

 

 

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blynskey_thinci
Observer
Observer
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Registered: ‎07-25-2018

Would it be possible for a Xilinx employee to comment on this?

 

Best regards,

 

 - Brendan

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blynskey_thinci
Observer
Observer
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Registered: ‎07-25-2018

Please could someone from Xilinx reply?

 

 - Brendan

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blynskey_thinci
Observer
Observer
429 Views
Registered: ‎07-25-2018

Any help at all from Xilinx on this would be appreciated.

 

If you don't know, please say so, so I can move on.

 

Best regards,

 

 - Brendan

 

 

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