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Visitor
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Registered: ‎06-11-2018

Zynq Ultrascale+ with Samsung LPDDR4, no ODT at DQ lines

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We are trying to get running a new board of us with Xilinx Zynq Ultrascale+ and Samsung LPDDR4 (1GB).

We have problems with RAM access. The levels of DQ signals during write accesses measured with high speed Osciloskop are at 1.1 V, the levels of CA lines are correct at about 0.6 V.

This means, ODT is enabled on CA but not enabled at DQ. The value written to MR11 by Xilinx SDK is 0x56 (ODT: RZQ/6 for DQ und RZQ/5 for CA).

Writing to register MR11 manually has no effect at DQ-ODT lines, at CA-ODT it has.

What can we do to get the ODT on DQ lines activated?

 

Xilinx has marked our type of Samsung LPDDR4 marked as tested with Zynq Ultrascale+. So how got they running the LPDDR4? Have the setpoints of the Samsung LPDDR4 been written and if yes, how?

 

Regards

Wolfram Fitting

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Moderator
Moderator
1,196 Views
Registered: ‎06-29-2011

The LPDDR4 spec was ambiguous here with relation to the following table.

odt_table.JPG

Memory device vendors Samsung, Hynix and Nanya interpreted N/A to mean no ODT, and Micron interpreted it to mean N/A latency, but ODT still turns on. So for the lower frequencies the ODT on the DQ pins is not enabled with Samsung, Hynix and Nanya memory devices.

There is a request with JEDEC to make this clearer for LPDDR5.

Note that as indicated in the Table Samsung, Hynix and Nanya do turn on ODT for 1600 Mb/s, with WL Set “B”. This can be accomplished by setting PSU__DDRC__VENDOR_PART approprately as per below.

Samsung devices: PSU__DDRC__VENDOR_PART = SAMSUNG
Hynix devices: PSU__DDRC__VENDOR_PART = HYNIX
Nanya devices: PSU__DDRC__VENDOR_PART = HYNIX

This can be done in the Vivado Block Properties section for the Zynq US+ MPSoC block or running the following Tcl command which will be also seen in the Tcl console if you change this in the Block Properties section. Please find my simple example below.

Tcl Command:

set_property CONFIG.PSU__DDRC__VENDOR_PART SAMSUNG [get_bd_cells /zynq_ultra_ps_e_0]

Vivado Block Properties:

vendor_settings.JPG

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

Kind regards,
Gareth

View solution in original post

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Moderator
Moderator
1,260 Views
Registered: ‎06-29-2011

Hi @init 

As I am already supporting this question for you using another support path I will take this question offline and will update the forum thread when we have a solution.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

Kind regards,
Gareth
0 Kudos
Reply
Moderator
Moderator
1,197 Views
Registered: ‎06-29-2011

The LPDDR4 spec was ambiguous here with relation to the following table.

odt_table.JPG

Memory device vendors Samsung, Hynix and Nanya interpreted N/A to mean no ODT, and Micron interpreted it to mean N/A latency, but ODT still turns on. So for the lower frequencies the ODT on the DQ pins is not enabled with Samsung, Hynix and Nanya memory devices.

There is a request with JEDEC to make this clearer for LPDDR5.

Note that as indicated in the Table Samsung, Hynix and Nanya do turn on ODT for 1600 Mb/s, with WL Set “B”. This can be accomplished by setting PSU__DDRC__VENDOR_PART approprately as per below.

Samsung devices: PSU__DDRC__VENDOR_PART = SAMSUNG
Hynix devices: PSU__DDRC__VENDOR_PART = HYNIX
Nanya devices: PSU__DDRC__VENDOR_PART = HYNIX

This can be done in the Vivado Block Properties section for the Zynq US+ MPSoC block or running the following Tcl command which will be also seen in the Tcl console if you change this in the Block Properties section. Please find my simple example below.

Tcl Command:

set_property CONFIG.PSU__DDRC__VENDOR_PART SAMSUNG [get_bd_cells /zynq_ultra_ps_e_0]

Vivado Block Properties:

vendor_settings.JPG

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

Kind regards,
Gareth

View solution in original post