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Contributor
Contributor
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Registered: ‎09-05-2018

Zynq & DDR3 - queries regarding write leveling of DQ and length matching

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According to various documents it is desired to keep DQS and associated data lanes shorter than CK to allow the write levelling process to occur.

I have two questions.  I am using a single x16 DDR3 chip in point-to-point configuration with an XC7Z010.  The CK pair and ADDR/CTRL bus are all 52mm +/-1mm.  The D1 byte is 30mm +/- 0.5mm.  And the D0 byte is 45mm +/- 0.5mm.

Is this configuration acceptable? (D0 < D1, both less than CK, D0 much closer to CK than D1)

What is the allowed range of variation from CK?  The spec just says "shorter" - at an 800MHz clock this would put the data buses less than one clock period behind CK, so it seems OK, but I wanted to verify as I could not find a specific requirement anywhere.

Finally I would also like to confirm that RESET is not length sensitive. I see some docs that suggest to keep it within ADDR/CTRL length, and others that say it is only used during initialisation, so length matching is not too important.

Thanks

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Moderator
Moderator
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Registered: ‎11-28-2016

Hello @tom667 ,

Yes, this is an acceptable configuration. As long as the CK traces are longer than the DQS then you will be fine.
The calibration routine treats every byte separately so the relative skew differences between the different byte lanes doesn't matter.
The spec just says shorter because with the limited topology support in the Zynq-7000 PS DDR controller you would have to intentionally make a very unreasonable layout in order to get close to the max value. Any reasonable person with a reasonable layout shouldn't have an issue in this area.

As for the DDR_DRST_B signal I wouldn't be concerned with length matching. Yes, it's only used in an early part of the DDR initialization and is not sensitive to a timing relationship with CK.

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Moderator
Moderator
388 Views
Registered: ‎11-28-2016

Hello @tom667 ,

Yes, this is an acceptable configuration. As long as the CK traces are longer than the DQS then you will be fine.
The calibration routine treats every byte separately so the relative skew differences between the different byte lanes doesn't matter.
The spec just says shorter because with the limited topology support in the Zynq-7000 PS DDR controller you would have to intentionally make a very unreasonable layout in order to get close to the max value. Any reasonable person with a reasonable layout shouldn't have an issue in this area.

As for the DDR_DRST_B signal I wouldn't be concerned with length matching. Yes, it's only used in an early part of the DDR initialization and is not sensitive to a timing relationship with CK.

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Contributor
Contributor
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Registered: ‎09-05-2018

Thanks for the confirmation! 

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