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marcoventurini
Adventurer
Adventurer
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Registered: ‎10-02-2014

Zynq ultrascale + max DDR clock

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Hello, I have a simple question about the DDR4 speed of the ZYNQ ultrascale devices,

In the datasheet i DS925 i found that the bandwidth of the DDR4 chip can be up to 1066 Mb/s  on a  SBVA484E package.

Vivado will not allow me to set more that 533Mhz  on the DDR clock speed.

I'm assuming that the speed of the ram (why in Megabits/s???, it should be MHz...) has to be multiplied by the bus size... am I correct?

So with a 16bits wide chip the max DDR speed is 2132 Mbytes/s... right?

Thanks,

Marco

marcoventurini_0-1624983671850.png

 

 

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barriet
Xilinx Employee
Xilinx Employee
317 Views
Registered: ‎08-13-2007

The memory is DDR - double data rate - so the convention commonly used is Mb/s which is 2x the clock rate since two bits are transferred every clock... This is implied per bit - so the rate is regardless of the DQ width (e.g. 16-bits, 32-bit, 80-bits, etc.)...

So as you've seen, 533MHz = 1066Mbps.


A throughput calculation would likely be in MB/s (Bytes, not bits) and involve the memory width, transfer length, other overhead, etc.

Cheers,
bt

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barriet
Xilinx Employee
Xilinx Employee
318 Views
Registered: ‎08-13-2007

The memory is DDR - double data rate - so the convention commonly used is Mb/s which is 2x the clock rate since two bits are transferred every clock... This is implied per bit - so the rate is regardless of the DQ width (e.g. 16-bits, 32-bit, 80-bits, etc.)...

So as you've seen, 533MHz = 1066Mbps.


A throughput calculation would likely be in MB/s (Bytes, not bits) and involve the memory width, transfer length, other overhead, etc.

Cheers,
bt

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marcoventurini
Adventurer
Adventurer
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Registered: ‎10-02-2014

Clear, the data in the table is just twice the max clock speed.

Thanks,

Marco

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marcoventurini
Adventurer
Adventurer
247 Views
Registered: ‎10-02-2014

One more thing,

Now if I set 500 Mhz on the DDR clock

marcoventurini_0-1625063431216.png

I see that the DDR clock inside the SOC is divided by 2

marcoventurini_1-1625063527304.png

What is the internal DDR clock used for? Is the 2:1 ratio correct?

I'm asking since I'm testing a Zynq ultrascale evaluation board and I get roughly one fourth of the bandwidth that I expect, while when i did the same test on a 7 series zynq I was able to almost reach the max bandwidth of the DDR chip.

Thanks

 

 

 

 

 

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