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385 Views
Registered: ‎05-29-2020

Zynq without DDR memory power supply design

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Hi everyone,

I'm about to design a Zynq XC7Z012S custom board for a customer, who doesn't want to have any DDR memory on the board at all.

My question would be: with the above mentioned scenario, can I simply connect the following signals to 1V8 or better leave them floating?

- VCCO_1.5V/1.8V
- VCCO_DDR

Thank you in advance!

Greetings,
Peter

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Xilinx Employee
Xilinx Employee
324 Views
Registered: ‎03-04-2018

Hello @peter_szilagyi ,

 

Both VCCO are connected to FPGA if not using the DDR memory.  UG1085 describes that.

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

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Xilinx Employee
Xilinx Employee
325 Views
Registered: ‎03-04-2018

Hello @peter_szilagyi ,

 

Both VCCO are connected to FPGA if not using the DDR memory.  UG1085 describes that.

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

-------------------------------------------------------

Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.  Please Give Kudos.

-------------------------------------------------------

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ddr4.PNG
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320 Views
Registered: ‎05-29-2020

Hi @kshimizu ,

You mean GND, right?

Greetings,
Peter

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Xilinx Employee
Xilinx Employee
311 Views
Registered: ‎03-04-2018

Hello @peter_szilagyi ,

 

Please connect to GND.

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

-------------------------------------------------------

Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.  Please Give Kudos.

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257 Views
Registered: ‎05-29-2020

Hi @kshimizu,

I couldn't not notice that both UG1085 and UG1075 (documents recommended by you) regard Zynq UltraScale+ processors. I couldn't find the same information in the documents of Zynq-7000. Can you confirm if it applies to that family as well?

Many thanks!

Cheers,
Peter

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