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Registered: ‎08-13-2018

Zynq7 slow qspi boot

Hello and thank you very much for taking the time clicking on this topic!

I'm having trouble with the following hardware:
A xc7z030fbg676-1 connected to a qspi-x4 (mt25ql256aba8e12-1sit) flash memory. 

I'm trying to do the following:
Boot a simple FPGA project (blinking a LED in VHDL) from the qspi flash memory on powerup.

I've tried:
I've generated a bitfile, build an FSBL according to the hardware, created a MCS file. 

What is happening:
The FPGA project runs perfect after it is done booting, HOORAY! however it takes a very very long time booting, it takes whopping 1.2 seconds.

Things to consider.
I've attached an image with a graph displaying the QSPI_CLK. It doesn't look like anything I would expect. The process seems to consists of three parts: a 5.4Mhz part for ~75ms (FSBL?), a pause for another 75ms and finally a 10.4Mhz part for about a whole second.

The QSPI clock frequency is set to 83.3334Mhz in the Zynq_processing_system IP and 66 Mhz in the .xdc file, bitsream compression is off and it is in QSPI_x4 mode. 

I've checked the IO_PLL and it seems to be running at the right frequency.

Let me know if there is more information I could provide!

Cheers and have a happy day!

Plot of the QSPI_CLK over timePlot of the QSPI_CLK over time


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2 Replies
Registered: ‎08-13-2018

The Qspi flash is running at a much higher frequency now, 83 Mhz during the second stage. setting XQSPIPS_CLK_PRESCALE_16 in qspi.c to XQSPIPS_CLK_PRESCALE_2 helped a lot. However, booting still takes a very very long time (700ms instead of >1s).

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Xilinx Employee
Xilinx Employee
Registered: ‎10-12-2018

Hi @lacsapix ,

How have you created boot image using SDK or petalinux?

First need to identify in which step it is taking more time than expected in the booting process. like BootROM, FSBL, u-boot?

Please refer below AR for QSPI boot times and optimization techniques.

Thanks & Regards
Anil B
Don’t forget to reply, kudo, and accept as solution.
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