abnormal phenomena of MIG 7Series

[yhm]

Hi, all,

These days, I designed and tested the MIG 7Series of DDR3 SDRAM on the ACDC1.0 board.

I deal with the MIG 7Series by AXI bus.

In my test design, first ,  write a data on one address of SDRAM, second, read the data of the address continuously so that the chipscope can detect the data.

There is an abnormal phenomena when test.

The chipscopes indicates that the data is correct most of the time,

However sometimes the data is not correct and it will be normal later. The phenomena runs in cycles.

I do not know why? Or I do not provide enough information?

Thanks in advance!

Regards

yhm

[vsrunga]

Hi,

I would suggest to test using MIG example design and see the status error signal.

If it is not seen then it could be your AXI/other blocks timing issue.

Regards,

Vanitha

[yhm]

Thanks for your advice.

I saved some pictures detected by the chipscope:

1, The data detected by the chipscope is correct. ( read the data of one address continuously )

2, Abnormal phenomena, two pictures, (read the data of one address continuously )

It seems that the timing issue?

Thanks again.

yhm

[vsrunga · Accepted solution]

Hi,

Is this your own data or MIG traffic gen's?

As said earlier please run MIG example design and monitir the error status

Regards,

Vanitha