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Registered: ‎10-09-2018

artix 7- MIG ref_clk connected to gnd

Hello,

system- Artix 7, ISE 14.7, WIN 10.

Lang- VHDL

 

I am using MIG IP Core and driving SYS_CLK with 200 MHz.

MIG generic:

CLKIN_PERIOD          : integer := 5000;
                                     -- Input Clock Period
   CLKFBOUT_MULT         : integer := 4;
                                     -- write PLL VCO multiplier
   DIVCLK_DIVIDE         : integer := 1;
                                     -- write PLL VCO divisor
   CLKOUT0_PHASE         : real    := 337.5;
                                     -- Phase for PLL output clock (CLKOUT0)
   CLKOUT0_DIVIDE        : integer := 2;
                                     -- VCO output divisor for PLL output clock (CLKOUT0)
   CLKOUT1_DIVIDE        : integer := 2;
                                     -- VCO output divisor for PLL output clock (CLKOUT1)
   CLKOUT2_DIVIDE        : integer := 32;
                                     -- VCO output divisor for PLL output clock (CLKOUT2)
   CLKOUT3_DIVIDE        : integer := 8;

 

I guess it is becoming 800 MHz as per requirement ,and for REF_CLK I have selected " USE SYSTEM CLK", but I am getting following error:

ERROR:Xst:2033 - Port I of Input buffer mig_inst/u_iodelay_ctrl/se_clk_ref.u_ibufg_clk_ref is connected to GND
ERROR:Xst:1847 - Design checking failed

I checked other generated files which are in verilog type(mig_7series_v1_9_iodelay_ctrl.v and some others also),but that files parameter not change accroding to ip core.

module mig_7series_v1_9_iodelay_ctrl #
  (
   parameter TCQ              = 100,
                                // clk->out delay (sim only)
   parameter IODELAY_GRP      = "IODELAY_MIG",
                                // May be assigned unique name when
                                // multiple IP cores used in design
   parameter REFCLK_TYPE      = "DIFFERENTIAL",
                                // Reference clock type
                                // "DIFFERENTIAL","SINGLE_ENDED"
                                // NO_BUFFER, USE_SYSTEM_CLOCK
   parameter SYSCLK_TYPE      = "DIFFERENTIAL",
                                // input clock type
                                // DIFFERENTIAL, SINGLE_ENDED,
                                // NO_BUFFER
   parameter SYS_RST_PORT     = "FALSE",
                                // "TRUE" - if pin is selected for sys_rst 
				//          and IBUF will be instantiated.
                                // "FALSE" - if pin is not selected for sys_rst
   parameter RST_ACT_LOW      = 1,
                                // Reset input polarity
                                // (0 = active high, 1 = active low)
   parameter DIFF_TERM_REFCLK = "TRUE"
                              // Differential Termination
   )

So I was trying to find out but not got what i wanted, Why this connected to GND error is coming?

 

-----

Even I try to give same CLK source directly to both the SYS_CLK & REF_CLK which is in the same coloumn, but that gives following error.

 

ERROR:ConstraintSystem:59 - Constraint <NET "sys_clk_i" TNM_NET = TNM_sys_clk;>
[top.ucf(26)]: NET "sys_clk_i" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.

-----

or if i use clocking wizard to generate two clocks and give them separately to SYS_CLK & REF_CLK, it gives follwing error:

ERROR:NgdBuild:455 - logical net 'CLK_OUT2_s' has multiple driver(s):
     pin CLKOUT1 on block pll_inst1/plle2_adv_inst with type PLLE2_ADV,
     pin PAD on block CLK_OUT2_s with type PAD

Does anybody know this issue?

 

Regards,

Avinash

 

 

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Scholar
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Registered: ‎08-07-2014

@avinashc,

How are you driving the sys_clk_i?

If it exists, can you re-check if it is connected correctly all the all from top-level to the ibufg_clk_ref?

Also make sure the definition exists and is correct for sys_clk_i inside the constraints file.

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Registered: ‎10-09-2018

Hello @dpaul24 ,

This is my constraint here

NET "sys_clk_i" TNM_NET = TNM_sys_clk;
TIMESPEC "TS_sys_clk" = PERIOD "TNM_sys_clk" 5 ns;

NET "sys_clk_i" CLOCK_DEDICATED_ROUTE = BACKBONE;
PIN "*/u_ddr3_infrastructure/plle2_i.CLKIN1" CLOCK_DEDICATED_ROUTE = BACKBONE;

NET   "sys_clk_i"                              LOC = "Y18"     |   IOSTANDARD = LVCMOS18             ; 


and i am driving to mig user_design

       sys_clk_i                       => sys_clk_i,

and I haven't change anything in core files, So i guessed I have done right.

 

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Registered: ‎08-07-2014

@avinashc,

I meant are you toggling the clock from the test-bench?

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Registered: ‎10-09-2018

Hello @dpaul24 ,


@dpaul24 wrote:

@avinashc,

I meant are you toggling the clock from the test-bench?


No, I am not driving currently anything from test bench.

 

---

If I use Clocking wizard with 2 outputs each for sys_clk(400 MHz) and ref_clk(200 MHz) and comment the  buffer of ref_clk as input after tracing through mig in " iodelay_ctrl.v " It works ( I have just replaced buffer part with assign statement after tracing ref_clk from mig.vhd) , But I read somewhere using pll thing is not ideal solution because of jitter issue.

--

so i was using sys_clk 200 MHz and ref clk is " use_sys_clk" in MIG IP Core. Even if I comment this buffer as I have done above case i am geting following error,but this cleared "connected to gnd" error as i have commented buffer part in iodelayctrl.v

 

ERROR:LIT:693 - Block 'MMCME2_ADV symbol
   "mig_inst/u_ddr3_infrastructure/gen_mmcm.mmcm_i"' has its target frequency,
   FVCO, out of range. Valid FVCO range varies depending on speed grade: 600MHz
   - 1200MHz(-1), 600MHz - 1440MHz(-2), 600MHz - 1600MHz(-3). The computed FCVO
   is a function of the input frequency CLKIN1_PERIOD, the division factor
   DIVCLK_DIVIDE, and the CLKFBOUT_MULT_F attribute (FVCO =
   1000*CLKFBOUT_MULT_F/(CLKIN1_PERIOD*DIVCLK_DIVIDE)). The CLKIN_PERIOD
   attribute may have been set by ngdbuild based on the user specified PERIOD
   constraint. The current calculated FVCO is 400.000000 MHz.

 

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Registered: ‎08-07-2014

@avinashc,

No, I am not driving currently anything from test bench.

Stop! One minute.....we need to discuss in steps.

Can you successfully run a simulation using the MIG?

The eg_design comes with a TB from where the sys_clk is toggled. Do you see this happening?

PLL/MMCM can come in later.

 

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Hello @dpaul24 ,

 

No my simulation is giving error. It's not even opening

ERROR: at 0 fs: Signal phy_dout index is out of bound.

ERROR: ERROR: The simulation failed to launch for the following reason:
   The Simulation shut down unexpectedly during initialization.  Please review the ISim log (isim.log) for details.
Please shut down ISim and retry the simulation.  If the problem persists, please contact Xilinx support.
Time resolution is 1 fs
No active Database
Unable to execute live simulation command.

The simulation has terminated.

I tried with user design as top_module , and I tried with example design & it's tb file also as top_module. In both cases ISIM is giving problem.

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Hello @dpaul24 ,

 

Now I tried with Verilog as default lang for my whole project . It works.

simulation is happening.

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Registered: ‎08-07-2014

@avinashc,

simulation is happening.

That is not a very useful info.

Do you see the init_calibration_complete signal going high? Do u see data being written by the core and the same data read out?

If both of them are yes, then just run synthesis of the design, nothing else. Do u still get the error of the system clk signal?

 

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Hello @dpaul24 ,

No, init_calibration_complete is not asserted.

1.jpg

I changed to Verilog for simulation puropse, Systhesize is done. 

Implementation has some error, but that should not affect simulation.

 

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@avinashc,

No, init_calibration_complete is not asserted

This signal of prime importance. You need to find out the reason why and fix it.

The MIG spec has some troubleshooting tips when the init_calibration_complete is not asserted. Try to use them.

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Hello @dpaul24 ,

Sorry for late reply as I was busy in other code.

 init_calibration_complete is asserting ,but its asserting after so much time(104 us) in simulation and i did not procedded that much in previous simulation.

But it is having some problem as i am sending sig from TB to drive data from my top module logic block ,as i am giving my data to ddr3 as below:

always @ (posedge clk)
  begin : FSM
//  if (reset == 1'b1) begin
//    
//  end else
   case(state)
     IDLE :  
	         begin
				app_wdf_rdy_ack <= 1'b0; 
				 app_rdy_ack <= 1'b0; 
	           if (wr_data == 1'b1) begin  //this signal i am giving from tb and then fsm gets start.           
					  app_addr     <= app_addr + 1'b1;  //28'b0;          //28'b0;
                 app_cmd     <= 3'b0;
					  app_wdf_data <= app_wdf_data + 1'b1;   //128'b0;          //16'b0;
			        app_wdf_wren <= 1'b1;          //1'b1;
					  app_wdf_end  <= 1'b1;   
					  app_en <= 1'b1; 
//                 app_hi_pri <= 1'b1; 	// not showing this sig in entity			  
					  state <= wr1;     end
				  else if(rd_data == 1'b1) begin
				     state <= rd1;
					  app_cmd     <= 3'b1;  end
			   end
              
     wr1 :  
	         begin
				 if (app_wdf_rdy ==1'b1) begin
	            
//				   app_wdf_data <= app_wdf_data + 1'b1;   //128'b0;          //16'b0;
//			      app_wdf_wren <= 1'b1;          //1'b1;
//					app_wdf_end  <= 1'b1; 
                 app_wdf_wren <= 1'b0;          //1'b1;
					  app_wdf_end  <= 1'b0;   
					  app_wdf_rdy_ack <= 1'b1;    // user logic sig
                                   end
				  if (app_rdy ==1'b1) begin
	             app_en <= 1'b0; 
//                app_hi_pri <= 1'b0;					 
//				   app_wdf_data <= app_wdf_data + 1'b1;   //128'b0;          //16'b0;
//			      app_wdf_wren <= 1'b1;          //1'b1;
//					app_wdf_end  <= 1'b1;   
					 app_rdy_ack <= 1'b1;  // user logic sig         // strobe for app cmd & en 
                                     end
					if (app_wdf_rdy_ack ==1'b1 && app_rdy_ack == 1'b1 ) begin      // we can check or condition here
	                   
					      state <= IDLE;        
                           end							 
												 
					
            end
	  wr2 :
	        begin
			   if (app_rdy == 1'b1) begin
				   state <= IDLE; end
				 
			  end
     rd1 : 
	            state <= IDLE;
	           
     default : state <=  #1  IDLE;
  endcase
  end

2.jpg

but in this case my app_rdy is getting asserted and deasserting after some toggles to remain deasserted.

I just want to know is my way of driving data is fine according to ug_586 waveform mentioned in pg no 124,125?

 

Thanks!

 

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