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Visitor
Visitor
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Registered: ‎10-19-2018

axi dma configuration and usage in verilog

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Hi,

i am using Vcu1525 board.

I want to access DDR4 memory, i know for that i have to use DDR4 SDRAM MIG IP.

I have my custom hardware IP in slave and master stream interface, I want my master stream interface to send data to ddr and read when required, whereas DDR4 MIG ip is slave axi4 full.

i am not able to figure out what should i do to talk to axi4 full.

here are some options i think:-

1) make a new axi4 full master(i have no idea how it works, though familier with axi4-lite)

2) use axi datamover IP

3) use axi cdma

4) use axi dma

 

i though to use axi dma, but not able to figure out how to configure and initialise wr/rd request in verilog, i found a ton of references in c language using zynq.

is there any example reference or any step by step guide which shows which axi lite regs to wr/rd for dma config and how to initialise wr/rd transaction, just any bare simple application will do, no need in SG mode for dma.

 

Thanks.

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Visitor
Visitor
337 Views
Registered: ‎10-19-2018

@calebd 

Hi,

Thank you for your response,

now, i did understand use of dma, and i saw in dma datasheets, it shows usage of axi data mover inside, i read axi data mover document and using example design i was able to understand how commands are made and handle status of transaction and also understood how data comes out of stream, i made 1 ip with slave axi lite interface,

master stream cmd interface,

slave stream sts interface,

slave stream mm2s interface,

below i have attached my schematic, and i tested from application in c using microblaze.

i am writing to ddr from microblaze and reading from datamover and route data back to axilite and read from axilite and print.

viola, i got what i needed.

Thanks.

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Scholar
Scholar
475 Views
Registered: ‎05-21-2015

@shazlokh786,

Two options come to mind.

  1. Xilinx has a virtual FIFO IP core that you can use
  2. There's also a similar open source alternative, which you could use to build something more off of.

Dan

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Visitor
Visitor
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Registered: ‎10-19-2018
thank you for your response.

I am planning to make a custom master axi full interface so i can have control when to write to ddr and at what address to read.

is there any reference design for master axi full,currently i am using vivado IP generator for master interface to get familier.

Thanks
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Moderator
Moderator
349 Views
Registered: ‎01-09-2019

@shazlokh786 

In regards to configuring the AXI DMA using a custom HDL master, that isn't quite how you usually use AXI DMA.  AXI DMA is a register/software-programmable IP that uses the Datamover IP to handle direct memory access which, once programmed, the transactions are independent of your processor.  We provide a few C examples that are based on a Zynq platform, but you could potentially convert over to a Microblaze based software stack and run the programming on that processor architecture.  These are the AXI DMA example software designs that we provide: https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/axidma/examples

The Datamover IP would be another option that would allow you to send AXI Streaming data directly to memory over an AXI Full interface, and this would be what would require a custom IP to program the commands for which you would need to create in your HDL of choice.  The convenience of the AXI DMA IP is that the HDL for actually programming the IP appropriately has already been completed and all you need to do is handle this from a software perspective.

These are the options that I would say are quite commonly used to send Streaming transactions to memory.

Thanks,
Caleb
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Visitor
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Registered: ‎10-19-2018

@calebd 

Hi,

Thank you for your response,

now, i did understand use of dma, and i saw in dma datasheets, it shows usage of axi data mover inside, i read axi data mover document and using example design i was able to understand how commands are made and handle status of transaction and also understood how data comes out of stream, i made 1 ip with slave axi lite interface,

master stream cmd interface,

slave stream sts interface,

slave stream mm2s interface,

below i have attached my schematic, and i tested from application in c using microblaze.

i am writing to ddr from microblaze and reading from datamover and route data back to axilite and read from axilite and print.

viola, i got what i needed.

Thanks.

View solution in original post

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