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simple.wang
Visitor
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Registered: ‎08-26-2014

axi-interconnect connect to MIG ddr3: simulation problem???(block design)

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AXI interconnect (2 slave + 1 master) and  MIG  ddr3    simulation   pass    in IP catalog  ,

but  simulation   nopass by  block design .The  data input   AXI interconnect   but  cannot output to MIG ddr3,why?


I hope somebody can help me.

Thanks very much.

Simple

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simple.wang
Visitor
Visitor
19,449 Views
Registered: ‎08-26-2014
Hi Vanitha,
Thanks,
added addr offset in addr editor and chnaged areset,block design sim pass.
Regards
Simple

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7 Replies
siktap
Scholar
Scholar
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Registered: ‎06-14-2012

Hi Simple

Have your generated the outputs after validating your design?

 

Regards

Sikta

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simple.wang
Visitor
Visitor
12,165 Views
Registered: ‎08-26-2014
AXI interconnect (1slave + 1 master) and MIG ddr3 simulation pass in block design, why not pass 2 to1 interconnect ?
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simple.wang
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Visitor
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Registered: ‎08-26-2014
Hi Sikta,
Generate output products,but have critical Warnings :Address block <mig..../memaddr> is not mapped into a Mater Address space.
Regards
Simple
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simple.wang
Visitor
Visitor
12,156 Views
Registered: ‎08-26-2014
Hi Sikta,

1 to 1 AXI interconnect have the critical Warnings

Regards
Simple
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simple.wang
Visitor
Visitor
12,146 Views
Registered: ‎08-26-2014
Hi Sikta,
The data transfer to mmu but mmu ouputs wrong in vivado 14.3 .
The data teansfer to arbit but arbit outputs wrong in vivado 13.2.
Regards
Simple
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vsrunga
Xilinx Employee
Xilinx Employee
12,114 Views
Registered: ‎07-11-2011

Hi,

 

By not passing you mean

Are you unable to write AXI interconect/AXI MIG is not ready ?  or

Able to write but the core is not responding for reads? or

Able to write and read but data do not match?

 

Please provide a block diagram description and elaborate the issue along with snapshots of relavant signals.

Do cross check if the connectivity and clock are proper, address mapping is correct.

 

-Vanitha

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simple.wang
Visitor
Visitor
19,450 Views
Registered: ‎08-26-2014
Hi Vanitha,
Thanks,
added addr offset in addr editor and chnaged areset,block design sim pass.
Regards
Simple

View solution in original post

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