11-24-2014 04:12 AM
AXI interconnect (2 slave + 1 master) and MIG ddr3 simulation pass in IP catalog ,
but simulation nopass by block design .The data input AXI interconnect but cannot output to MIG ddr3,why?
I hope somebody can help me.
Thanks very much.
11-24-2014 05:06 AM
11-24-2014 05:35 AM
11-25-2014 03:31 AM - edited 11-25-2014 03:32 AM
By not passing you mean
Are you unable to write AXI interconect/AXI MIG is not ready ? or
Able to write but the core is not responding for reads? or
Able to write and read but data do not match?
Please provide a block diagram description and elaborate the issue along with snapshots of relavant signals.
Do cross check if the connectivity and clock are proper, address mapping is correct.