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sraza
Explorer
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Registered: ‎03-13-2012

can there be 1 or 2 empty cycle delay between two halves of BL8 transfer for DDr3

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hello all,

 

I have tried to explain my problem in the question...Can it be like this that, we have 1 or 2 (for example)  cycle delay between two cycles of BL-8 transfer, i.e. 1st cycle trasnsfer, then 1 clock delay (due to unintentional reasons like buffer fifo I have made gets empty or otherwise)  then resume the second half of app_wdf_data transfer along with app_wdf_end gets HIGH...is it correct and appropriate...

 

hope this helps

 

thanks in advance

 

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vsrunga
Xilinx Employee
Xilinx Employee
11,590 Views
Registered: ‎07-11-2011

Hi ,

 

So in this case to provide oen burst to DDR you need to write two UI data words(each X64), worst case you will be having a clock 1 or 2 clocks delay between them ? I believ it is allowed.

Make sure that command is issued after(within 2 clocks)  the burst data is provided.

You may simulate this and read back the data for double confirmation.

 

Out of curiousity I ran a quick simulation figure 1 shows the writes with a clock delay and figure 2 reads the same data, it seems working.

 

Hope this helps.

 

Regards,

Vanitha.

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MIG_UI_1.png
MIG_UI_2.png
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vsrunga
Xilinx Employee
Xilinx Employee
8,461 Views
Registered: ‎07-11-2011

Hi,

 

Do you mean at UI or DDR physical interface ?

At physical interface I believe it cannot be. In the sense that 1 or 2 cycles where you cannot load data will be driven either Zeros or existing values on the bus.

 

If this is at UI,  it depends on your app_data_width, memory configuration etc.,

You have gating signals like app_wdf_en, app_wdf_end.

If you can satisy the timing diagram figure 4-32  of UG586, page 529  then i think there should not be any issue.

 

Hope this helps.

 

Regards,

Vanitha.

 

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UI_timing.png
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sraza
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thank you for your response...

 

Yes I mean UI

what I wanted to ask is this same thing that if we have empty clock cycle between first and second Half of BL-8 transfer, and in the second half definitely we give the app_wdf_end as well even after 1 clock cycle..hope you understand.

 

since waveform can tell better here is one for you to understand what I am confuse about....^_^

In the first image you can see the blue part, that is what I am talking about.

The second image is the clean image w/o any editing...thanks

 

edited.JPG original.JPG

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vsrunga
Xilinx Employee
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Registered: ‎07-11-2011

Hi,

 

ok, I am assuming it is 7series, can you provide your memory frequency, memory data width, nCK_PER_CLK/app_data_width so that we can decide?

 

Regards,

Vanitha.

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sraza
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Thank you for your response...

 

I am using virtex-6 FPGA with DDR3 (micron technology : DDR3-1333)

 

hence I suposse the the frequency is 666MHz

app_data_width  is 29 bits (although in actual it should be 28 bits, since there is only 1 rank, but MIG generate by defualt 1 bit for rank as well...any ways I think it did not affect the design as this is common I have read this same forum)

 

btw. I have found some clue in the ui_wr_data.vhd ...

I saw the comments for app_wdf_rdy signal and it was written(among other information)

 

-- If we see the first getting accepted, then

-- second half is unconditionally accepted.

 

  wr_req_16             : OUT  STD_LOGIC;

 

-- case ({wr_data_end, rd_data_upd_indx_r})

-- block: occupied_counter

-- Keep track of how many write requests are in the memory controller. We
-- must limit this to 16 because we only have that many data_buf_addrs to
-- hand out. Since the memory controller queue and the write data buffer
-- queue are distinct, the number of valid entries can be different.
-- Throttle request acceptance once there are sixteen write requests in
-- the memory controller. Note that there is still a requirement
-- for a write reqeusts corresponding write data to be written into the
-- write data queue with two states of the request.
wr_req_16 : OUT STD_LOGIC;

 

but please do share if you know something else, since this is only  a hint to my question, not actual answer. 

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vsrunga
Xilinx Employee
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Registered: ‎07-11-2011

Hi,

 

Can you provide your memory data width and app_data_width ?

 

Regards,

Vanitha.

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sraza
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memory width is 16x

while app_wdf_data is 16*4 = 64 bit

 

memory rwo address  : 16 bit

col : 10 bit

bank : 3 bit

rank : nonte(single

 

app_addr width : 29 bit

(512 MB memory)

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vsrunga
Xilinx Employee
Xilinx Employee
11,591 Views
Registered: ‎07-11-2011

Hi ,

 

So in this case to provide oen burst to DDR you need to write two UI data words(each X64), worst case you will be having a clock 1 or 2 clocks delay between them ? I believ it is allowed.

Make sure that command is issued after(within 2 clocks)  the burst data is provided.

You may simulate this and read back the data for double confirmation.

 

Out of curiousity I ran a quick simulation figure 1 shows the writes with a clock delay and figure 2 reads the same data, it seems working.

 

Hope this helps.

 

Regards,

Vanitha.

---------------------------------------------------------------------------------------------
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Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

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MIG_UI_1.png
MIG_UI_2.png
sraza
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Registered: ‎03-13-2012

thank you for your efforts and time

 

I really appreciate it

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sraza
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Registered: ‎03-13-2012

 

hello quoting your reply

Make sure that command is issued after(within 2 clocks)  the burst data is provided.


I read in the ug406, pg.122 that 

 

When issuing back-to-back write commands, there is no maximum delay between the write data and the
associated back-to-back write command, as shown in Figure 1-64.

 

(you can see delay between  ADDRe command and data-e is more than 2 clock cycle, and more for ADDR-f)

Actually my intention is to use back-to-Back write

b2b_write.JPG

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vsrunga
Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

Hi,

 

Yes, you can go ahead continuously for back 2 back writes as long  as app_wdf_rdy signal is asserted.

Good Luck!

 

 

Regards,

Vanitha.

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