03-13-2013 06:23 AM
I am confused regarding the DDR3 MIG design for virtex 6. I am using ug406 as the reference and please help me with this quote which has confused me is this quote:
The UI resembles a simple FIFO interface and always returns the data in order.
So My questions are:
1. First of all I am only using User interface and connecting all my custom design's PINs w.r.t User Interface rather Native. Since I am not using Native interface does it means that the DDR3 design that I am using now behaves merely as FIFO.
03-13-2013 12:54 PM
Yes. What it's trying to say is that order you send commands to the User Interface (UI) is not necessarily the same order that the controller wil send to the DDR3. The controller can reorder your commands to achieve higher bus efficiency and then will return data in the same order you sent them so from a user perspective it behaves as a simple FIFO.
The native interface will not return data in the order you sent it so it relies on the user design for reordering.
03-13-2013 09:17 PM
Thank you for your reply.
Ok now I understand, but pardon me one more clarification (although I think I have understood) that unlike FIFO we can access our data multiple time (i.e. in FIFO if we read data once, the read pointer moves down and we cannot read it twice).