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Participant
Participant
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Registered: ‎12-28-2014

custom LPDDR2 and Zynq

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We are checking out a first PCB run of a Zynq 7Z045 and a LPDDR2.

My first step in bringup was to build the DRAM test in SDK and it passed perfectly.  After kernel panics on boot in Linux, I went back and started testing memory regions and found that I could not address any memory at 0x04000000 or higher.

The LPDDR2 connections are as shown below (we referenced the discussion at https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Zynq-LPDDR2-DQ-Swap-Question/td-p/396867 as we were swapping DQ bands 1 & 2.

ram.png

Next, to configuring the PS DDR controller.  The LPDDR2 data sheet states: "Each of the x32’s 536,870,912-bit banks is or-
ganized as 16,384 rows by 1024 columns by 32 bits."  I would take this as banks of 512Mb, 3 bit bank addressing (4G part), 14 bit row addressing, 10 bit column addressing, although I'm not sure how important this is as LPDDR2 only uses 10 bit addressing and PS_DDR_BAx is not used.  Anyhow, these were the values used in the PS config menu:

cfg.png

I'm not strictly confident in the values of CAS latency, RAS to CAS, Precharge Time, tRC, tRASmin, tFAW.  The EDB data sheet table:

134b_2e0e_embedded_lpddr2.png

If there are some LPDDR2 experts that could suggest anything I would greatly appreciate it! I would really like to understand why addressing beyond 64M stalls the system (and below a certain memory location, assuming this is where the ELF is located. I have no issues with FSBL and U-BOOT. Thanks.

 

EDIT: I did mistake the field DRAM Device Capacity for the individual bank size, and of course 512Mb would be 64MB.  I have increased this field to 4096Mb but do experience memory errors - Guidance on the other parameters would be greatly appreciated.

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Participant
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Registered: ‎12-28-2014

A follow up for anybody interested in interfacing the EDB4432BBBJ LPDDR2 - I had success bringing up this ram by noticing that the default 32 bit part in the DDR configuration menu, MT42L64M32, had the same parameters in their datasheets.  Using the values from the configuration menu for the default part:

RAS to CAS Delay - 7

Precharge Time - 8

tRC - 63

tRASmin - 42

tFAW 50

These values worked well. memtest success to 512GB and booted Linux.  And of course changed the DRAM Device Capacity to 4096Mb and Col Address Count (bits) to 10.

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Participant
Participant
1,043 Views
Registered: ‎12-28-2014

A follow up for anybody interested in interfacing the EDB4432BBBJ LPDDR2 - I had success bringing up this ram by noticing that the default 32 bit part in the DDR configuration menu, MT42L64M32, had the same parameters in their datasheets.  Using the values from the configuration menu for the default part:

RAS to CAS Delay - 7

Precharge Time - 8

tRC - 63

tRASmin - 42

tFAW 50

These values worked well. memtest success to 512GB and booted Linux.  And of course changed the DRAM Device Capacity to 4096Mb and Col Address Count (bits) to 10.

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Newbie
Newbie
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Registered: ‎04-09-2020

Hi,

  Would you please post the whole screen cut of the ram configuration in the block design?  I am not sure the parameters I used in the EDB1316BDBH-1DIT-F is correct since the the ram can not work correct(SDK shows can not read the correct data, the data write is 55AA,but the data read back is 0)

 

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