cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Observer
Observer
10,097 Views
Registered: ‎07-09-2014

custom traffic suggestions

Jump to solution

Hi everyone 

 

This message has a previous question. Click

When I do the DDR3 simulation I commented out the example design"traffic generator" and wrote a simple state machine which only write and read once.

here is part of my code.

idle:begin
 if(done==1)           //wait for init_calib_complete finish
  next<=wr_ac;
 else
  next<=idle;
end

wr_ac:begin         //write address,cmd and assert app_en until app_rdy assert
 if(app_rdy==1)
  next<=wr_data;
 else 
  next<=wr_ac;
end

wr_data&colon;begin    //write 576bits data once
 next<=stop;     //assert "app_wdf_wren" and "app_wdf_end"
end

stop:begin
 if(counter==10)     //wait for counter 10 cycles
  next<=read_d;
 else
  next<=stop;
end

read_d:begin 
 if(app_rdy==1)     // write address,cmd, and assert app_en until app_rdy assert
  next<=wait_d;
 else
  next<=read_d;
 end

wait_d:begin        //wait for app_rd_data
 next<=wait_d;
end

 If I wrote app_wdf_data as "app_wdf_data=576'h0000000000000000_0000000000001234_0000000000004321_0000000000000abc_0000000000000cba_00000000000001a1_00000000000002a2_00000000000003b3_00000000000004b4;"

 

the app_rd_data was strange,such like

 

simu2.jpg

 

I do not know the reason.

 

Best Regards

Jack

0 Kudos
Reply
1 Solution

Accepted Solutions
Observer
Observer
17,102 Views
Registered: ‎07-09-2014
Thank you Vanitha
Finally I finished by myself.
The app_wdf_data must be given with the address and command together.

Best Regards
Jack

View solution in original post

0 Kudos
Reply
7 Replies
Xilinx Employee
Xilinx Employee
10,092 Views
Registered: ‎08-01-2008


To change the data and command patterns properly, follow these steps:

  1. Set DATA_PATTERN and CMD_PATTERN in sim_tb_top.v/vhd.
  2. Set modify_enable_sel=0 in example_top.v.
  3. Set DATA_MODE and CMD_PATTERN in init_mem_pattern_ctr.v/vhd.

Starting in the ISE 13.3 release, uses will only have to modify CMD_PATTERN and DATA_PATTERN in sim_tb_top to change the command and data patterns for their simulation.
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos
Reply
Observer
Observer
10,089 Views
Registered: ‎07-09-2014
Thank you Balkrishan
As I know, DATA_PATTERN and CMD_PATTERN are traffic generator parameters.
However, I made a traffic by myself. I think these 2 parameters have no relationship with my traffic.

Best Regards
Jack
0 Kudos
Reply
Xilinx Employee
Xilinx Employee
10,084 Views
Registered: ‎07-11-2011

Hi,

 

Please upload yor mig.prj, xdc and your simulation waveform in vcd format fo analysis

 

Regards,

Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
0 Kudos
Reply
Observer
Observer
17,103 Views
Registered: ‎07-09-2014
Thank you Vanitha
Finally I finished by myself.
The app_wdf_data must be given with the address and command together.

Best Regards
Jack

View solution in original post

0 Kudos
Reply
Xilinx Employee
Xilinx Employee
10,074 Views
Registered: ‎07-11-2011

Hi,

 

Glad that the issue is resolved.

If you remeber I think that is what I said in my earlier post to follow the timing diagrams in UG586

 

 

Regards,

Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
0 Kudos
Reply
Observer
Observer
10,069 Views
Registered: ‎07-09-2014
Hi Vanitha

That is true. I am confused because of the "back-to-back"
In burst mode, data seems can not delay for 2 cycles.

Thank you a lot for helping me.

Best Regards
Jack
0 Kudos
Reply
Scholar
Scholar
5,555 Views
Registered: ‎08-07-2014

 Hi,

 

I am also working on a custom logic that drives the UI. After reading this thread, I am a bit confused.

 

ug586, Pg 163, the timing diagram and text says that write data & its corresponding signals can be triggered upto 2 clk cycles *before and after* the addr & write_cmd has been placed for it to be successfully buffered insid ethe MIG FIFO

 

But the jackdo20  mentions initially:

The app_wdf_data must be given with the address and command together.

 

Then in the end he mentions:

That is true. I am confused because of the "back-to-back"
In burst mode, data seems can not delay for 2 cycles.

 

Now that looks conflicting to me! What is correct, can anyone please explain?

 

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem

0 Kudos
Reply