cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
sraza
Explorer
Explorer
8,361 Views
Registered: ‎03-13-2012

data shifting for writing INTO DDR3 using MIG

Jump to solution

hi thank you very much 

 
I have one very irritating results and for which I cannot sort out why, coz it is generated internal to MIG? So if you find some free time and can have a look at it I would be thankful for your suggestion over it
 
I am operating at clk_mem = 300 Mhz and clk = 150 Mhz and have data shifting while wiring. You can see the image in the figrure below whenre I have shown the difference between actual data and the shifting value. After some singnals this shifting increase more (but I have noticed it is only in multiples of 8).
Hence I would like you guys help in figuring out what is the problem here since I urgently have to submit the results for my thesis and this is the fundamental step :(
 
I have tried to summarize it as:
 
1. In each case, signals on app_wdf_data were same as I expected but when I checked the wr_data_rise0, wr_data_fall0, wr_data_rise1, wr_data_fall1 in phy of MIG, I found that I get shifted signals there. I have tried to show in the image below
 
3. So can u know of any reason of this behaviour and data shift as I should say, it appears like in some inner buffer the data seems to store (like for example in FIFO, and it comes the new coming data. But why and how to trace down the problem.)
 
Thanks for your time.
 
Bests,
ShanSIGNAL DIFFERENCES.JPG
0 Kudos
1 Solution

Accepted Solutions
sraza
Explorer
Explorer
13,948 Views
Registered: ‎03-13-2012
Thank you very much for your help and I am able to solve the problem.
 
 
There were some issues in my design, last addresses at few occasions were not fed since the app_rdy was low and at the same time, the system refresh command issued by me was activated which take the system to new state for next data generation etc..
 
bests,
Shan

View solution in original post

0 Kudos
3 Replies
vsrunga
Xilinx Employee
Xilinx Employee
8,356 Views
Registered: ‎07-11-2011

Hi,

 

By data shifting do you mean bytes/words in a burst are shifted or data shfted with respect to address?

Can you share us the vcd, mig.prj and ucf for invetigation?

 

Regards,

Vanitha.

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
0 Kudos
vsrunga
Xilinx Employee
Xilinx Employee
8,350 Views
Registered: ‎07-11-2011

Hi,

 

If your waveforms are same to that of below post where you mentioned the issue was cleared with clock changes

 

http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/partial-data-corruption-while-DDR3-read/td-p/382179

 

but In your waveforms I see you are issuing write command before write data is filled in the FIFO please check if you are doing this knowingly, this may cause zeros to be written in those address locations.

 

Command and Data can be delayed by 1 or 2 clocks but not more than that, try to issue write command at the instance you started data writing with app_wdf_wren = '1' and recheck the behavior.

 

Hope this helps.

 

 

Regards,

Vanitha.

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
0 Kudos
sraza
Explorer
Explorer
13,949 Views
Registered: ‎03-13-2012
Thank you very much for your help and I am able to solve the problem.
 
 
There were some issues in my design, last addresses at few occasions were not fed since the app_rdy was low and at the same time, the system refresh command issued by me was activated which take the system to new state for next data generation etc..
 
bests,
Shan

View solution in original post

0 Kudos