cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
291 Views
Registered: ‎04-06-2017

ddr3_reset_n byte group in MIG IP

Jump to solution

In my MIG IP design, I have 24 address/ctrl pins and 22 data pins. I assign them in one of the HP bank of Kintex-7 FPGA. I set T0 and T1 for address/ctrl pins , T2 and T4 for data pins. I set the data speed to 1600 bps so that one vref in T0 byte group is used as external vref. Now I have 23 pin in T0 and T1 for address/ctrl pins. I observe the automatical assignment that ddr3_reset_n is assigned at T2 which is for the data pins. I validate the assignment using MIG wizard, the outcome is good. I am not sure whether it is ok because ddr3_reset_n is a control pin. I hope someone can tell me. Thank you.

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Teacher
Teacher
283 Views
Registered: ‎06-16-2013

Hi @greatmaverick 

 

ddr3_reset_n signal is used during initialize sequence.

And it is asynchrnous reset signal.

So, it's OK at T2.

 

Best regards,

View solution in original post

1 Reply
Highlighted
Teacher
Teacher
284 Views
Registered: ‎06-16-2013

Hi @greatmaverick 

 

ddr3_reset_n signal is used during initialize sequence.

And it is asynchrnous reset signal.

So, it's OK at T2.

 

Best regards,

View solution in original post