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sraza
Explorer
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Registered: ‎03-13-2012

debugging MIG based desing for DDR3 communication (using chipscope)

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Hello every one,

 

I am designing the DDR3 based system using virtex-6 FPGA and I am able to completely send all my data to DDR3. I know this thing coz I have checked signals (like app_wdf_data, app_addr, an other customized signals etc.) using chipscope which tells me that communication is fine...But since I cannot connect DDR3 external ports I was never sure if data actually went INTO ddr3, now that I check using read data path...All I get is garbage data...Even now I check app_rd_data, app_read_data_valid etc. signals. for read data path

 

suggest me how to connect the DQ signals to chipscope since they are external ports hence they cannot be connected. Also please suggest me where and how to start debugging from since it is my first time with this intense stuff.(of course I am also trying, but expert opnion will save effort and help me do things faster since my deadline is only 5 days from now)

 

Bests,

Jaffry

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sraza
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Registered: ‎03-13-2012

I am not 100% sure if this is the right answer or not, but I have found atleast in my design that once in hardware when phy_init gets HIGH it means the caliberation is DONE. The same is written in the ug406 as well. Hence I am not considering the states of phy_rdlv and phy_wrlvl states now, atleast according to my understanding. 

 

Any experienced guy can add further for others to avail benefit

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yenigal
Xilinx Employee
Xilinx Employee
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Registered: ‎02-06-2013

 

Hi Jaffry,

 

Did you tried the traffic patterns available in the example design and seeing the same issue in reads or this is only seen with your custom data input.

 

I suggest you to try the Traffic generator available with the example design which send and reads back the data from the DDR3.

 

use it as a reference and compare how you are driving the data.

 

Have a look at the below AR's which will guide you in debugging the data errors.

 

http://www.xilinx.com/support/answers/34588.html

http://www.xilinx.com/support/answers/35218.html

http://www.xilinx.com/support/answers/34709.html

 

If the issue is seen with example design also,post the simulation VCD for further analysis.

 

Hope it helps,

 

Regards,

Satish

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sraza
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Registered: ‎03-13-2012

Thank you for replies...

 

 

I have went through the posts and several other links and got more confused...

 

1. Since there is no calibrration, (but phy_init_done) is  HIGH, I am figurring if the deisgn is communicating with the DDR3 at all?

 

2. I have found using from the design guide the following line for caliberation that

 

The ports that need a setting are:
dlyval_dq_offset    
dlyval_dq_wr_offset 
rd_bitslip_cnt      
rd_clkdly_cnt       
rd_active_dly       
rd_clkdiv_inv   

 

Hence I am looking for the working for these ports, but in the meanwhile any reference will be appreciated. Please answer the first question if possible. Also note that I have looked the write data path using chipscope up until the last point where the chipsopce can be connected before actual IO port and I see valid going inside...

 

Thanks

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vsrunga
Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

Hi,

 

If Phy_init_done is high DDR3 calibration is done and ready to use.

 

When calibration is successful I believe there is no necessity to consider the below signals status the next step is to monitor app_* signals.

 

lyval_dq_offset    
dlyval_dq_wr_offset 
rd_bitslip_cnt      
rd_clkdly_cnt       
rd_active_dly       
rd_clkdiv_inv  

 

Please go through UG586, you can find the timing diagrams for write and read into DDR3.

 

-Vanitha.

 

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sraza
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Registered: ‎03-13-2012

thank you

 

Pardon me I think I will take some more time of yours now since results are not 

 

You mean that those signals are only during the caliberation process. After that they are not needed...OK

 

but even though my phy_init_done is HIGH, but I do not have phy_rdlvl_done(0) and phy_rdlvl_done(1) both is LOW...i.e. as far as I undeststand they should be HIGH throughout once they are HIGH after read leveling done once.

 

Note that data that I have received from the DDR3 is following. Which you can see in either 0 or other DUMMY data...so why is it so I cant understand. Any idea?

.

data_captured.JPG

 

 

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vsrunga
Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

Hi,

 

So you say phy_init_done is high but calibration is not done!!!

I believe you could not connect DQ signals to chipscope due to timing and routing issues.

Can you see the same behavior in simulation or on Hardware only ?

Could you find out the failure calibration stage with the help of below Xilinx AR  and then capture the signals of interest for further analysis

 

http://www.xilinx.com/support/answers/35169.html

 

Regards,

Vanitha.

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sraza
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Registered: ‎03-13-2012

 

So you say phy_init_done is high but calibration is not done!!!

 


at least this is what I have understood. Note that I am checking the signals over chipscopre only and am not going through or have done hardware-co simulation ( the things are fine on functional simulation).

 

I believe you could not connect DQ signals to chipscope due to timing and routing issues.


Yes definitely since DQ signals are the external ports which cannot be connected to chipscope.

 

I have gone through your link and that too shows that phy_init will get HIGH after all stages are gone through so I have an idea that after the read and write leveling are done, and is phy_init are done HIGH, those signals become '0' again...So ' I guess ' calibearation is all right.  right ?

 

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vsrunga
Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

Hi,

 

I do not think once *_done is asserted it will be cleared after init_done goes high.

You may check the same behavior in functional simulation for confirmity.

 

What is the status of app_rdy, can you export all the signals into a vcd and upload here ?

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sraza
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Registered: ‎03-13-2012

I am not 100% sure if this is the right answer or not, but I have found atleast in my design that once in hardware when phy_init gets HIGH it means the caliberation is DONE. The same is written in the ug406 as well. Hence I am not considering the states of phy_rdlv and phy_wrlvl states now, atleast according to my understanding. 

 

Any experienced guy can add further for others to avail benefit

View solution in original post

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