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vincenttrinh
Observer
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Registered: ‎10-02-2018

example MIG test design with ATG

Hi,

We created an example test design with the ATG.  Our controller is setup as 32bit DDR3. VIO_ATG_EN is defined.  I had a look at https://www.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf, but it is not clear to me how to run the tests.  Can someone post step-by-step instruction on how to run the various tests?

For example, on page 769, it says to set vio_tg_instr_addr_mode to TG_PATTERN_MODE_LINEAR, but I could not find out the value of TG_PATTERN_MODE_LINEAR.  I could also not find values for TG_PATTERN_MODE_PRBS, TG_RW_MODE_WRITE_READ, TG_VICTIM_MODE_NO_VICTIM.

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kren
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Registered: ‎08-21-2007

It means the vio_tg_instr_addr_mode is set to 0  for linear address pattern You can find the description of this signal in Table 38-45 on page 765.

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vincenttrinh
Observer
Observer
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Registered: ‎10-02-2018

OK,

Thanks for pointing out the table.  Is it possible to provide step-by-step instructions on how to run the various tests?

 

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vincenttrinh
Observer
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Registered: ‎10-02-2018

Hi,

To clarify our intent here.  We want to run the ATG tests to make sure there are no issues with signal integrity or board level issues.

We are working with a custom DDR controller from a third party, and we see occasional errors.  The third party wants use to run these tests to try to exclude signal integrity or board level issues.

Thank you.

 

kren
Moderator
Moderator
844 Views
Registered: ‎08-21-2007

For the step-by -step instructionss, you can talke a look at the "How to Program Traffic Generator Instruction" section on pages 566-567.

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vincenttrinh
Observer
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Registered: ‎10-02-2018

Hi,

I did the following step:

vio_tg_start to 0, vio_tg_pause to 1

vio_tg_restart to 1, vio_tg_restart to 0

vio_tg_err_chk_en to 1

vio_tg_direct_instr_en to 1

vio_tg_instr_num[4:0] to 0

vio_tg_instr_addr_mode[3:0] to 0

vio_tg_instr_data_mode[3:0] to 1

vio_tg_instr_rw_mode[3:0] to 2

vio_tg_instr_rw_submode[1:0] to 0

vio_tg_instr_victim_mode[2:0] to 0

vio_tg_instr_victim_select[2:0] to 0

vio_tg_instr_victim_aggr_delay[4:0] to 0

vio_tg_instr_num_of_iter[31:0] to 0001_0000

vio_tg_instr_m_nops_btw_n_burst_m[9:0] to 0

vio_tg_instr_m_nops_btw_n_burst_n[31:0] to 0000_0010

vio_tg_instr_nxt_instr[5:0] to 0

vio_tg_pause to 0

vio_tg_start to 1

set trigger in hw_ila_1, trigger if vio_tg_status_err_bit_valid == 1

The ILA never triggers.

Does this mean the test is successful?  i.e. there is no error?

 

 

 

 

 

 

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kren
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Registered: ‎08-21-2007

Did you capture the user interfacesignals of the MIG IP and check the write/read operation? If so and the data_compare_error was not asserted, it indicated no data error was found with this customized traffic. 

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vincenttrinh
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Registered: ‎10-02-2018

Can you tell me how to "check the write/read operation"?

 

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calebd
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Registered: ‎01-09-2019

@vincenttrinh 

I believe what @kren is mentioning here is that you should ensure that the reads and writes match with the configuration that you have set up (i.e. if you are doing linear sequential addressing then the addresses should increase by 1 for each write or read).  Can you confirm that your address and data accesses are following the pattern you are attempting to configure using the VIOs?

It may also be beneficial to start with testing using the initialized BRAM table which has preset commands for running traffic.  This can be found in the file titled "ddr4_v2_2_8_tg_instr_bram".

Thanks,

Caleb


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vincenttrinh
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Registered: ‎10-02-2018

Hi,

I was asking how exactly do I verify the read/write operation manually.  What signals/data should I look at?  Unfortunately, I am not very familiar with DDR signal, so if there was a step-by-step instruction, that would be very useful.

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calebd
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Registered: ‎01-09-2019

@vincenttrinh 

This would depend slightly on your configuration, but if you have an AXI interface you would need to check AXI spec. (the ARM documentation can be found here: https://developer.arm.com/documentation/ihi0022/d ).  If you have a User/Application interface you can find that documentation in PG150 on page 122 and onwards.

Either way, you would check based on the specific protocol whether the data and address you are writing match the data and address as you read it back.  A simple first test would be to start with a Linear data pattern (starting at 0x0, 0x1, 0x2,...) and a Linear addressing pattern (0x0, 0x1, 0x2,...).  You can set these by looking at the tg_instr_bram.sv file I pointed at earlier.  The table in that file will need to be edited and you will need to know which DEFAULT_MODE you are running in (in the basic version I believe this is 2015_1 mode based on tg_top).

Thanks,

Caleb


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