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Newbie lihongfei
Registered: ‎11-07-2011

hi,I have a question of the DDR3 demo

hello, when I use the ip core demo of the mig3.6 ,but there is not axi_mcb.v and mcb_ui_top_synch at the core files. At the example_top it is not include to mig_3_6.v why?
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Registered: ‎07-21-2009

Re: hi,I have a question of the DDR3 demo

Unfortunately, you don't mention which FPGA family you are targeting.  The MIG output is *very* different for the various different FPGA families.  Oh well...


Here's an excerpt from the Spartan-6 FPGA Memory Solutions UG416 doc (v1.5):


Click the Enable AXI check box to add an AXI4 user interface to all MCBs (this option is only available for Verilog designs). Otherwise, the MIG design is generated with the standard (or Native) user interface by default.


I imagine the checkbox for AVI4 vs. 'native' is replicated somehow when using MIG for other FPGA families.  I'll let you do the 'digging' on this.  Then there's the Verilog vs. VHDL election...


Hope this helps!


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