cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
peter_092
Visitor
Visitor
9,608 Views
Registered: ‎04-26-2013

how to set a multi-chip DDR controller?

hi there,

 

I am going to set a DDR controller connenting to 4 DDR chips, with a Virtex-6 chip LX240T and ISE14.4 enviroment. The IP-Core Generator gives a solution of 4 times data width and one set of CS and ADDRESS wires driving 4 DDR chips. But I want to get a controller that fits the 4 chips with commmon ADDRESS wires but seperate CS and DATA. So I can read or write  data from or into a unique chip at different time using different CS controls and same ADDRESS wires.

 

Is there such a IP-Core fitting the requst, or should I write a DDR controller module myself?

0 Kudos
5 Replies
vsrunga
Xilinx Employee
Xilinx Employee
9,604 Views
Registered: ‎07-11-2011

Hi,

 

You can have multiport options in MCB(s6), but in V6 MIG if you go for Multi controller it gives independent address, data, cs etc.,

If you want shared address bus but common data then you can increase data width in MIG data width drop down and connect the same controller to different chips, but it will not have have different CS and the entire memory is treated as single chip with increased data width like DIMM

 

One way is you can have AXI Interconnect on top of MIG and allocate address range as needed

 

Please check below link on similar discusison

http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/multiport-lpddr2-on-Artix-7/td-p/367763

 

Hope this helps

 

-Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
0 Kudos
yenigal
Xilinx Employee
Xilinx Employee
9,601 Views
Registered: ‎02-06-2013

Hi

 

NO this is not available

 

You need to generated seperated controllers if you want the functionality.

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
0 Kudos
peter_092
Visitor
Visitor
9,581 Views
Registered: ‎04-26-2013

Hi Vanitha,

 

Thanks for your replay. I have metioned that "The IP-Core Generator gives a solution of 4 times data width and one set of CS and ADDRESS wires driving 4 DDR chips. " Maybe my description is not clear enough but I mean what you said. 4 times of ADDRESS bus is too many for IO ports in my design so I want to share ADDRESS bus. Thank you all the same.

 

Best regards.

0 Kudos
peter_092
Visitor
Visitor
9,579 Views
Registered: ‎04-26-2013

Hi Satish,

 

Thanks a lot for your clear replay. But seperated controllers need seperated ADDRESS bus. 4 times of ADDRESS bus cost too IO ports in my design, so I want to share. I am looking for other solutions.

 

Best regards.

 

 

0 Kudos
vsrunga
Xilinx Employee
Xilinx Employee
9,560 Views
Registered: ‎07-11-2011

Hi,

 

Understood your requirement, but with multi controllers you cannot share address bus.

It is possible only with single controller and having multiple ports on top of it that share the common address.

Even in this approach it is true that physically there will be one address bus at AXI/UI side you feel that you are accessing different small chips as the commands will be time multiplexed at phy end.

 

If you can visit the link that I pinted in my earlier post you can get a overview on how to do it

 

Regards,

Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
0 Kudos