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harshalrode
Contributor
Contributor
2,954 Views
Registered: ‎10-01-2009

how to use mig 3.0 spartan 3E reference design for communicating to SDRAM

I successfully simulated the spartan 3E starter kit reference design.

 

But it is a design with synthesizable testbench.

 

Now I need to use sdram controller to store my data into SDRAM. I want to use this design but how to use it as controller only.

 

It doesnt have user_input_data and user_input_address kind of signals in top level entity. 

 

The design itself generates addresses and command fsm signals through entities in test bench therefore they cannot be  removed to store my data. But, at the same time... it is not easy to change the code to make it store external data.

 

Does anyone have a project on this? or idea about how this can be done?

 

Thanks

Harshal

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criley
Xilinx Employee
Xilinx Employee
2,899 Views
Registered: ‎08-16-2007

Are you looking for a stand-alone SDRAM Controller?

What memory type are you going to use (ex. DDR2, DDR3 etc.)?

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