11-18-2020 01:18 AM
Hello
Can you give me some advice on the implementation?
I used Xilinx Virtex®UltraScale+™ VU37P HBM FPGA. The placement and routing time was very long and often could not be passed. Is there any good method or appropriate strategy for faster and better layout and routing?
11-18-2020 09:10 PM
Hello @xifengw ,
Could you please try to do an example design in PG275. I have no experiences like that when creating an example design. Please compare between example and your design.
https://www.xilinx.com/support/documentation/ip_documentation/hbm/v1_0/pg276-axi-hbm.pdf
Best regards,
Kshimizu
Product Application Engineer Xilinx Technical Support
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