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Explorer
Explorer
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Registered: ‎04-19-2016

max addressable range of Zynq 7000 Processor via DDR3 interfaces

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Hello, 

 

*I am currently using Zynq 7000 series SoC. 

*At most, how much size is addressable by zynq processor, (in terms of DDR3 memory controller )? ( 1G ? )

*could I see a PL side DDR3 content via Memory tab in SDK in debug session ? Is it possible?

*I have a 2GB DDR3 in PL side. I am using MIG IP to reach it from PS side via AXI interface. So, how much of this space could be addressable by processor? 

 

Best Regards,

 

 

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Voyager
Voyager
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Registered: ‎06-24-2013

Hey @doner_t,

 

Check out the System-Level Adress Map (Table 4-1) of UG585.

 

At most, how much size is addressable by zynq processor, (in terms of DDR3 memory controller )?

The range available to DDR memory (via controller) is from 0000_0000 up to 3FFF_FFFF so 1GB max.

 

So, how much of this space could be addressable by processor?

PL side memory could be mapped into the address ranges from 4000_0000 up to BFFF_FFFF so a total of 2GB there.

 

Hope this clarifies,

Herbert

-------------- Yes, I do this for fun!

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Voyager
Voyager
6,390 Views
Registered: ‎06-24-2013

Hey @doner_t,

 

Check out the System-Level Adress Map (Table 4-1) of UG585.

 

At most, how much size is addressable by zynq processor, (in terms of DDR3 memory controller )?

The range available to DDR memory (via controller) is from 0000_0000 up to 3FFF_FFFF so 1GB max.

 

So, how much of this space could be addressable by processor?

PL side memory could be mapped into the address ranges from 4000_0000 up to BFFF_FFFF so a total of 2GB there.

 

Hope this clarifies,

Herbert

-------------- Yes, I do this for fun!

View solution in original post

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Explorer
Explorer
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Registered: ‎04-19-2016

Thank you @hpoetzl,

 

You can see address editor of design attached. I could not reach some of below address. I have received two types error below seen(attached). Except those errors, I could reach to remaining addresses succesfully via SDK.

 

  1. Error type : memory read error at 0x80000000. Memory read aborted. External abort. This error seen when I try to read below memories in SDK;
  • DDR3_IFC/mig_7series_0 [0x8000_0000 to 0x9FFF_FFFF], 
  • hdmi_out/v_tc_0 [0x43C3_0000 to 0x43C3_FFFF ]

2. Error type : memory read error at 0xA0000000. Timeout waiting for the  Instruction Complete bit. This error seen when I try to read below memories in SDK;

 

  • AXI_C2C/axi_chip2chip_0 [0xA000_0000 to 0xBFFF_FFFF]   ( S_AXI)
  • AXI_C2C/axi_chip2chip_0 [0x43C2_0000 to 0x43C2_FFFF]   (s_axi_lite)

 

QUESTIONS : 

  1. My address assignments are wrong?  Or what could be possible reasons of the above errors ? 
  2. Should I assign 2G memory size [0x4000_0000 to 0xBFFFF_FFFF ] to 'DDR3_IFC/mig_7series_0' , to reach my all 2GB PL side DDR3 memory via SDK ?
  3. Should I assign totally 1G memory size [ 0x0000_0000 to 0x3FFFF_FFFF ] to the all others s_axi_lite interfaces.  

 

Best Regards,

address_editor.JPG
IMG_1192.JPG
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Voyager
Voyager
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Registered: ‎06-24-2013

Hey @doner_t,

 

You can see address editor of design attached.

I see something there, but it is not very informative, as I do not know your block design :)

 

memory read error at 0x80000000. Memory read aborted. External abort.

memory read error at 0xA0000000. Timeout waiting for the Instruction Complete bit.

My address assignments are wrong?  Or what could be possible reasons of the above errors?

The range from 4000_0000 to 7FFF_FFFF is assigned to the first General Purpose Master Port (M_AXI_GP0) while the range from 8000_0000 to BFFF_FFFF is assigned to the second one (M_AXI_GP1). So it is essential that you attach all the bits between 4000_0000 and 7FFF_FFFF as Slave to M_AXI_GP0 and those between 8000_0000 and BFFF_FFFF to M_AXI_GP1.

 

Should I assign 2G memory size [0x4000_0000 to 0xBFFFF_FFFF ] to 'DDR3_IFC/mig_7series_0' , to reach my all 2GB PL side DDR3 memory via SDK?

You can do that if you want to have it all present at once, but it will use up the entire mapped address space for both master ports, so no other slaves would be reachable (including all the AXI-Lite slaves). Also note that you need to connect it to both master ports, otherwise only half of it will be visible.

 

Should I assign totally 1G memory size [ 0x0000_0000 to 0x3FFFF_FFFF ] to the all others s_axi_lite interfaces.

Assuming that you want to reach them from the PS side, you need to use addresses in one of the master port ranges to make them visible to the PS.

 

So given the 'new situation' that you have a bunch of AXI-Lite slaves as well as your 2G PL DDR memory, you need to decide if you want to sacrifice part of your additional 2G DDR mapping for the AXI-Lite slaves or if you do some banking for the DDR memory. For example you could use the first master port for all the AXI-Lite slaves and the second master port only for the PL DDR (or vice versa), which would give you access to 1G PL DDR at a time, but with banking, you could select which half of the 2G range is visible. Note that this can become tricky if you want to use the mapped memory in an operating system like Linux.

 

Hope this clarifies,

Herbert

-------------- Yes, I do this for fun!
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Explorer
Explorer
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Registered: ‎04-19-2016

Hello @hpoetzl

 

...For example you could use the first master port for all the AXI-Lite slaves and the second master port only for the PL DDR (or vice versa)...,

I do as you say above. I am using M_AXI_GP0 to reach all Axi-Lite slaves, and M_AXI_GP1 for the PL DDR[512M] and Axi-Chip2Chip IP[512M] via an (1 slave in, 2 master outs ) Axi-Interconnect IP. Problematic port is this M_AXI_GP1. I am going to check block-design connections between MIG and Axi-Chip2Chip and Axi-Interconnect IPs.  

 

Thank you,

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Voyager
Voyager
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Registered: ‎06-24-2013

Hey @doner_t,

 

The AXI-Lite interfaces do not look that intensive to me (from the address map) so it might also be an option to put the PL DRR on one AXI Master (with 1GB) and the Chip2Chip in one half of the other with all the AXI-Lite blocks.

 

The most generic arrangement is probably to use M_AXI_GP0 for the DDR and M_AXI_GP1 for Chip2Chip + AXI-Lite.

In this case, you can even run an OS like Linux on the full 2GB range (PS+PL DDR) without any special tricks.

 

All the best,

Herbert

-------------- Yes, I do this for fun!
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