12-13-2016 04:34 AM
I am trying own read write on a qdr2+ memory model(cyqdr2_b4, cypress). In example design it is taking about 28 us to give init_calib signal high. If i remove the traffic generator mig is not asserting init_calib.
My question is that the traffic generator is essential for init_calib or some other thin is missing?
12-13-2016 07:57 PM
No,calibration doesn't have any dependency on the traffic generator.
Traffic generator sends data only once the calibration is done.
12-14-2016 12:58 AM
Yes that's correct. I ran example design with traffic gen disabled along with all parameters and the calib signal came through.
Any insight on what i'm not taking under consideration in my test bench or design.