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yogesh_tripathi
Adventurer
Adventurer
3,127 Views
Registered: ‎06-27-2016

mig not giving init_calib high for qdr2+ memory model

Hi,

I am trying own read write on a qdr2+ memory model(cyqdr2_b4, cypress). In example design it is taking about 28 us to give init_calib signal high. If i remove the traffic generator mig is not asserting init_calib.

 

My question is that the traffic generator is essential for init_calib or some other thin is missing? 

 

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yenigal
Xilinx Employee
Xilinx Employee
3,097 Views
Registered: ‎02-06-2013

Hi

 

No,calibration doesn't have any dependency on the traffic generator.

 

Traffic generator sends data only once the calibration is done.

Regards,

Satish

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yogesh_tripathi
Adventurer
Adventurer
3,091 Views
Registered: ‎06-27-2016

Hi

Yes that's correct. I ran example design with traffic gen disabled along with  all parameters and the calib signal came through.

Any insight on what i'm not taking under consideration in my test bench or design.

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