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baparicio
Visitor
Visitor
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Registered: ‎11-08-2017

multiple access to DDR

Hi,

we are designing a system with 3 VDMAs writing and reading to DDR4 that in some cases can access to DDR4 simultaneously. We have found that some random errors happen when accessing to memory. By using CRCs we have checked that in occasions the data from one of the VDMAs is not written in DDR4. So, when this data is read again we have a non correct value. VDMAs status registers don't show any errors, and sometimes the system works. It seems to be related with number of "ones" in the data bus. 

Our DDR4 memory is MT40A256M16GE-083E, and it has passed the xilinx DDR test in the microblaze examples. 

It is possible that there is any conflict with the memory access so the data is lost? What could be the solution?

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kren
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Registered: ‎08-21-2007

Please first check whether the write data on the DDR4 IP interface is correct. That will help identify the problem is within or out of the controller.

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baparicio
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Registered: ‎11-08-2017

Hello,  thanks for yor answer, 

the data writen in the DDR4 IP interface is correct, we are writing images and have checked it by using CRC. That way we have detected that sometimes some of the pixels are not written.

In the architecture, the memory data bus width is 64 bits. To access the MIG controller, we use a AXI bus with data width:=512 

VDMAs sends pixels with a stream data width=128. 

Sometimes, pixels are not written. There is not any incorrect value instead, the thing is that those 128 bits are not written in memory. By looking VDMA interrupt registers we can see the bits have been sent. With an AXI performance monitor, we can check that those transactions have been done. The problem seems to be in the MIG controller. 

We are controlling also the Alert_n pin but it has no errors. 

Any idea? 

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