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daniel.cogan
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Registered: ‎07-30-2013

multiport lpddr2 on Artix-7

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The MIG for Spartan 6 allowed for a multiport configuration, whcih could be defined in the MIG.  The MIG for Artix-7 does not seem to have this.  Is there a different way to achieve a multiport configuration in the series 7 parts?

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daniel.cogan
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Registered: ‎07-30-2013

Thank you.  I think I'll summarize and then probably close the thread.

 

LPDDR2 is available in Vivado only using the 7 series MIG, and does not have the option for an AXI front end.  Series 7 MIG does not have multiport support.  Therefore, in order to add a multiport front end to the LPDDR2 controller, there are two options:  

 

1) Design a multiport arbiter which communicates directly to the "native" or "user" interfaces of the LPDDR2 controller.

or

2) Generate an AXI interconnect (similar to 7 series MPMC) with multiple slaves to be used as the user ports and one master to communicate with the controller.  Create a bridge module between the master port of AXI interconnect and the "native" or "user" interface of the controller.  [One suggestion is that this bridge may already exist in the AXI verion of DDR2 or DDR3, if it can be easily stripped out].

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vsrunga
Xilinx Employee
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Registered: ‎07-11-2011

Hi,

 

In standalone MIG you cannot do this but  I think EDK MPMC may help you.

 

Regards,

Vanitha.

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daniel.cogan
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Hi,

 

I looked at the MPMC v6.03.a.  It's dated March 2011.  Reading the introduction, it does not say it supports LPDDR2.  Is there a more recent version of MPMC which supports it?   Any other options?  Does the MIG for ISE support LPDDR2? (Seems like the older MIG had a multiport built in).

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vsrunga
Xilinx Employee
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Hi,

 

I think AXI_DDRX_7series do not support LPDDR2 but standalone MIG does in non-AXI mode, please check in ivado 2013.2.

 

 

Regards,

Vanitha.

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muzaffer
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The solution to get a MPMC in 7 series MIG seems to use an AXI interconnect with many slave ports (to connect to the many masters which need memory access) and 1 master port (to connect to the slave port of the mig)
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vsrunga
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Hi,

 

On further analysis It looks like Spartan-6 architecture is not possible by default in standalone MIG/EDK unless you add AXI switch on top of MIG generated DDR3 controller.

 

But I am not sure how would you benifit from multiports as DRAM has only one DQ port, so can do either write or read at a time.

 

 

Regards,

Vanitha.

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daniel.cogan
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Architecturally, it makes sense to have multiple user ports to a memory; different parts of the system need to access/share the memory at different times.  It's not meant to be truly in parallel (since one DQ port) but to parts of the system it "seems' that way.  Either we have to make a sharing mechanism to do that, or use a Xilinx component if possible.

 

I'll look into the MPMC in 7 series MIG. Thank you. I believe that LPDDR2 controller has a setting to use AXI.

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vsrunga
Xilinx Employee
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Hi,

 

It makes sense, but unfortunately LPDDR2 do not have AXI enabled in Vivado, so you might not be able to see it in EDK, you may recheck at your end and confirm this.

 

 

Regards,

Vanitha.

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daniel.cogan
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You're right.  That's unfortunate.  Looks like so far only DDR2 and DDR3 are supported for AXI.  Maybe I can make a bridge from AXI4 to the native user interface of LPDDR2 if nothing else.

daniel.cogan
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One more question on topic - Do you know if it's on the roadmap to have multi-port support in the 7 series MIG?  

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vsrunga
Xilinx Employee
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Hi,

 

Sorry but the answer is No, as Xilinx is moving towards  8series(Ultascale),  MIG 7 seris is almost frozen.

 

 

Regards,

Vanitha.

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daniel.cogan
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Thank you.  I think I'll summarize and then probably close the thread.

 

LPDDR2 is available in Vivado only using the 7 series MIG, and does not have the option for an AXI front end.  Series 7 MIG does not have multiport support.  Therefore, in order to add a multiport front end to the LPDDR2 controller, there are two options:  

 

1) Design a multiport arbiter which communicates directly to the "native" or "user" interfaces of the LPDDR2 controller.

or

2) Generate an AXI interconnect (similar to 7 series MPMC) with multiple slaves to be used as the user ports and one master to communicate with the controller.  Create a bridge module between the master port of AXI interconnect and the "native" or "user" interface of the controller.  [One suggestion is that this bridge may already exist in the AXI verion of DDR2 or DDR3, if it can be easily stripped out].

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vsrunga
Xilinx Employee
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Registered: ‎07-11-2011

Hi,

 

That's correct, thanks for your understanding and summarizing.

 

 

Regards,

Vanitha.

 

 

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