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JohnsonHu
Observer
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Registered: ‎08-13-2020

no DDR cycles as VDMA + DDR simulation

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Hi,

I'm verifying the VDMA + DDR in simulation, though the VDMA + SRAM runs well with the same video source and sink models.

1) Test Block Diagram

JohnsonHu_0-1612344790956.png

The DDR connection is refer to the MIG7 reference design, with 64-bit wide. 

"ddr3_model.sv", "ddr3_model_parameters.vh" are included in the simulation.

2) DDR Calibration: It takes about 55 us (the signal init_calib_complete from MIG7 is assert) 

JohnsonHu_1-1612344882618.png

3) VDMA -write cycles (axi_s2mm signals)

JohnsonHu_2-1612344950008.png

Q1. Why the VDMA-write transfer stops at the half way of the 4th burst ?   (s2mm_wready turns to be low)

Q2. As there are some wdata transferred, why the DDR3 bus is SILENT after calibration except the refresh cycles  ?

Johnson. FEB.3.2021

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JohnsonHu
Observer
Observer
259 Views
Registered: ‎08-13-2020

(update the simulation)

There are several issues if the VDMA stops after some burst among AXI bus.

Please check axi_bresp if the address-map is not valid (for interconnect). If so, use Address Editor to make the address valid.

Besides, it's recommend to select the AXI-interconnect option "debug" for enable AXI protocol checker. It would show any protocol error(s) among AXI-bus !

With these two issues resolved, there are DDR cycles visible.

Johnson

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JohnsonHu
Observer
Observer
260 Views
Registered: ‎08-13-2020

(update the simulation)

There are several issues if the VDMA stops after some burst among AXI bus.

Please check axi_bresp if the address-map is not valid (for interconnect). If so, use Address Editor to make the address valid.

Besides, it's recommend to select the AXI-interconnect option "debug" for enable AXI protocol checker. It would show any protocol error(s) among AXI-bus !

With these two issues resolved, there are DDR cycles visible.

Johnson

View solution in original post

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