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sanghyun_kim
Observer
Observer
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Registered: ‎02-17-2020

petalinux consideration about Zynq DDR access through PL

In ordinary OS, there is caching structure that Processor read cache memory first
and if that is different from DDR memory then copy data from DDR memory to cache by specific caching policy (drop least recently used, etc..).

 

my question is if PL write down some data to DDR memory, and next operations are exactly same with normal OS ?.
i means that can Petalinux recognize need to update cache memory when PS read DDR where writed by PL, without any additional PL side notifying (to OS) logic.

or is there additional implementation to notify "DDR data changed by PL"?

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ibaie
Xilinx Employee
Xilinx Employee
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Registered: ‎10-06-2016

Hi @sanghyun_kim 

Not sure if you are talking about Zynq-7000 or Zynq MPSoC device, but the capabilities on this use case are pretty different on them.

Zynq-7000: There is no coherency features between PL and APU, therefore any write operation to DDR performed by the PL means the APU needs to invalidate it's cache lines (or disable cache for shared address space).

Zynq MPSoC: There is a specific port S_AXI_ACE_FPD which is cache coherent, which allows the CCI to manage the coherency between APU and PL. In this case if configured properly the CCI will perform the cache maintenance operation so the APU does not need to invalidate the cache lines.


As you can see the PL does not really need to do anything in none of the cases. The coherency allows the APU to "forget" about maintenance, else it needs to be aware that shared resources needs to have flush or invalidate operations.

Regards


Ibai
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