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10,279 Views
Registered: ‎02-18-2016

problem with the netlist generation in edk which has mig interface

the target device is artix-7 and i am using xilinx ise14.7 version

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vsrunga
Xilinx Employee
Xilinx Employee
10,275 Views
Registered: ‎07-11-2011

@geethavaradaraju

Can you please elaboarate your problem with log files and snashots?

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10,273 Views
Registered: ‎02-18-2016

i have added the mig ip interfaced with the microblaze processor and trying to generate the netlist but i am getting error:3900 which MIG invoke error.....

edk_mig_error.jpg
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vsrunga
Xilinx Employee
Xilinx Employee
10,267 Views
Registered: ‎07-11-2011

@geethavaradaraju

 

Above the errors I see a message that  you have selected invalid time period, viist the IP GUI again and change the memory clock period in allaowed valid range and recheck

 

-Vanitha

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10,263 Views
Registered: ‎02-18-2016

i have set the edk to calculate the clk period and the frequency i have choosen is 400Mhz. here is the snapshot......

edk_clk_period.jpg
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vsrunga
Xilinx Employee
Xilinx Employee
10,255 Views
Registered: ‎07-11-2011

@geethavaradaraju

But 1250 is 800Mhz which does not match with your sleected 400Mhz, please check if external clock has a different frequency which can cause this behaviour.

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10,251 Views
Registered: ‎02-18-2016

external frequency is 100mhz out of which i am deriving 800Mhz with phase 337.5 for freq_refclk and mem_clk is 800Mhz which is 4*clk_ref.

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vsrunga
Xilinx Employee
Xilinx Employee
10,248 Views
Registered: ‎07-11-2011

@geethavaradaraju

Please generate 400Mhz and assign it mem_clk

 

You can refer table 1-61 for difefrent clock definitions

http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_4/ug586_7Series_MIS.pdf

 

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10,246 Views
Registered: ‎02-18-2016

even i tried that i am getting the following error which i have attached....

edk_mem_clk_error.jpg
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vsrunga
Xilinx Employee
Xilinx Employee
10,241 Views
Registered: ‎07-11-2011

@geethavaradaraju

 

Can you upload your system here?

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9,617 Views
Registered: ‎02-18-2016

PFA

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9,610 Views
Registered: ‎02-18-2016

Thank u vanitha for your support, my issue is resolved....

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vsrunga
Xilinx Employee
Xilinx Employee
9,603 Views
Registered: ‎07-11-2011

@geethavaradaraju

It is basically the clocking. Glad that the issue is resolved.

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Christian1
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Visitor
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Registered: ‎05-15-2020

Hello, how did you resolve it?

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