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gastonmelo1980
Contributor
Contributor
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Registered: ‎10-05-2018

sdr sdram MT48LC16M16 with spartan 6 write/rad burst

Hi to all, I know that this is an old devices, but I had an spartan-6 board with this sdram and Im trying to use it to store data coming from camera CMOS ov7670. I have a sdram controller and make a custom IP on SDK (ISE 14.6).

I can write and read to random location of the sdram, but when I try to use burst read/write (2,4 or the burst read only comes with 1 value (like the sdram only write the last value send it). The mod red has the next configuration:

   
   -- | A12-A10 |    A9    | A8  A7 | A6 A5 A4 |    A3    | A2 A1 A0 | 0 0 0 | 0 0 1 | 0 1 0 | 0 1 1 |
   -- | reserved| wr burst |op mode | CAS Ltncy|burst type| burst len|burst 1|burst 2|burst 4|burst 8|
   --   0  0  0      0       0   0    0  1  0       0      0  0  0
   constant MODE_REG : std_logic_vector(12 downto 0) := "000" & "0" & "00" & "001" & "0" & "001";

 

the address Im sending is 0x800300, and Im using the sdram to store values in 16 bits

 -- 23  22  | 21 20 19 18 17 16 15 14 13 12 11 10 09 | 08 07 06 05 04 03 02 01 00 |
 -- BS0 BS1 |        ROW (A12-A0)  8192 rows         |   COL (A8-A0)  512 cols    |	

 

in the SDk to perform a single write/read I use this code:

    	single_data = 0xAAAA;
    	single_write(single_data,0x800202);
    	while(write_finish != 0);
    	delay_us(1);
    	single_read(0x800202);
    	delay_us(1);

this are the subroutines to read/write single values:

void single_write(Xuint16 single_data,Xuint32 address)
{
	write_finish = 1;
    bu = MEMORY_CONTROLLER_mWriteReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG6_OFFSET, 0);
    bl = MEMORY_CONTROLLER_mWriteReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG7_OFFSET, 1);
	rw = MEMORY_CONTROLLER_mWriteReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG2_OFFSET, 1);
	we = MEMORY_CONTROLLER_mWriteReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG3_OFFSET, 0);
	addr = MEMORY_CONTROLLER_mWriteReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG4_OFFSET,address);
	single_to_sdram = MEMORY_CONTROLLER_mWriteReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG5_OFFSET, single_data);
	while(done!=1)
		done = MEMORY_CONTROLLER_mReadReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG9_OFFSET);
    while(done != 0)
    	done = MEMORY_CONTROLLER_mReadReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG9_OFFSET);
	return write_finish = 0;
}

void single_read(Xuint32 address)
{
    bu = MEMORY_CONTROLLER_mWriteReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG6_OFFSET, 0);
    bl = MEMORY_CONTROLLER_mWriteReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG7_OFFSET, 1);
    we = MEMORY_CONTROLLER_mWriteReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG3_OFFSET, 1);
    rw = MEMORY_CONTROLLER_mWriteReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG2_OFFSET, 1);
    addr = MEMORY_CONTROLLER_mWriteReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG4_OFFSET,address);
    while(done != 1)
        done = MEMORY_CONTROLLER_mReadReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG9_OFFSET);
    while(sdram_test != 1)
    	sdram_test = MEMORY_CONTROLLER_mReadReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG0_OFFSET);
    while(sdram_test != 0)
       sdram_test = MEMORY_CONTROLLER_mReadReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG0_OFFSET);
    while(done != 0)
    	done = MEMORY_CONTROLLER_mReadReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG9_OFFSET);
    single_from_sdram = MEMORY_CONTROLLER_mReadReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG10_OFFSET);
}

but to perform burst of length 2,4 or 8 i use this subroutines:

int write_sdram(Xuint16 *data,Xuint32 address)
{
	write_finish = 1;
    bu = MEMORY_CONTROLLER_mWriteReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG6_OFFSET, 0);
    bl = MEMORY_CONTROLLER_mWriteReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG7_OFFSET, 1);
	rw = MEMORY_CONTROLLER_mWriteReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG2_OFFSET, 1);
	we = MEMORY_CONTROLLER_mWriteReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG3_OFFSET, 0);
	addr = MEMORY_CONTROLLER_mWriteReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG4_OFFSET,address);
	for(j=0;j<2;j++){
		data_to_sdram[j] = MEMORY_CONTROLLER_mWriteReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG5_OFFSET, data[j]);
	}
	while(done!=1)
		done = MEMORY_CONTROLLER_mReadReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG9_OFFSET);
    while(done != 0)
    	done = MEMORY_CONTROLLER_mReadReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG9_OFFSET);

	return write_finish = 0;
}

void read_sdram(Xuint32 address)
{

    bu = MEMORY_CONTROLLER_mWriteReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG6_OFFSET, 0);
    bl = MEMORY_CONTROLLER_mWriteReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG7_OFFSET, 1);
    we = MEMORY_CONTROLLER_mWriteReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG3_OFFSET, 1);
    rw = MEMORY_CONTROLLER_mWriteReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG2_OFFSET, 1);
    addr = MEMORY_CONTROLLER_mWriteReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG4_OFFSET,address);
    while(done != 1)
        done = MEMORY_CONTROLLER_mReadReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG9_OFFSET);
    while(sdram_test != 1)
    	sdram_test = MEMORY_CONTROLLER_mReadReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG0_OFFSET);
    while(sdram_test != 0)
       sdram_test = MEMORY_CONTROLLER_mReadReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG0_OFFSET);
    while(done != 0)
    	done = MEMORY_CONTROLLER_mReadReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG9_OFFSET);
    //data_from_sdram = MEMORY_CONTROLLER_mReadReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG10_OFFSET);
    for(j=0;j<2;j++){
    data_from_sdram[j] = MEMORY_CONTROLLER_mReadReg(XPAR_MEMORY_CONTROLLER_0_BASEADDR, MEMORY_CONTROLLER_SLV_REG10_OFFSET);
    }
}

 

If im using burst length 2, the last bit of the address is used to select the column position (A0), the address A8-A1 is used to select the column and A21-A9 to select the Row. Sending the address 0x800300 im suing the row number 1, 8 column and position 0. But reading whats comes from sdram is the last value send it

    	data[0]=0xAAAA;
    	data[1]=0xBBBB;

always return 0xBBBB;

Maybe Im only writing 1 value to the sdram, but I use the mod_reg with those values (and according to datasheet is for Burst length 2). The only thing of my error is the reading and writing for burst length. Any help?

 

gastón

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