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nnjec
Visitor
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Registered: ‎01-08-2020

synchronization of DDR4 MIG PHY Command/address interface with external clock of 1200Mhz

Design Information:- 

 - FPGA Part - XCZU7EV-3FFVC1156 

 - Design is consists of the DDR4 MIG PHY-ONLY IP with the custom memory controller.

 - DDR interface is set up as 1200MHz (833 ps), DDR4 address/command/clock, and data bus are mapped on I/O Bank 64,65,66.

 - There is another External Input clock of 1200Mhz is incoming to FPGA at bank 28.

 

Question:- 

We want DDR4 interface(perticularly Command-Address interface) in-phase with External clock with around 100-200ps margin.

Is there any way to achieve this? Xilinx DDR4 PHY has cascaded MMCM and PLL. So, how to achieve this phase relationship between input clock and clock that is driving DDR4 interface?

from pg150from pg150

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rpr
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Registered: ‎11-09-2017

Hi @nnjec 

Generally, the range of external clock source would be between 70MHz - 700MHz. To find the exact value I recommend using the vivado tool. Configure the MIG with targeted interface frequency and check the supported clock source frequency range.

rpr_0-1623764698377.png

 

Regards
Pratap

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nnjec
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Registered: ‎01-08-2020

Hi @rpr,

Thanks for the reply.

about range of clock, we are using DDR4 MIG PHY-ONLY IP with RDIMM [ part - Mta18asf2g72pz-2g3] with Memory Interface Speed at 1200Mhz which allows reference clock Max 882 MHz as input as per Wizard Thats fine.

 

but Primary concern here is We want DDR4 interface(perticularly Command-Address interface) in-phase with Input clock with around 100-200ps margin. Is there any way to achieve this?

because Xilinx DDR4 PHY has cascaded MMCM and PLL. So, how to achieve this phase relationship between input clock and clock that is driving DDR4 interface?

 

Thanks,

- Nirav 

 

 

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kshimizu
Xilinx Employee
Xilinx Employee
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Registered: ‎03-04-2018

Hello @nnjec ,

 

I’m not sure why you think about the range between CAC and clock in syc within pico-second.  Xilinx MIG IP works well if it follows the guideline.

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

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nnjec
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Registered: ‎01-08-2020

Hi @kshimizu,

Thanks for the reply.

 

In this case, System's requirement is such that DDR4 interface(perticularly Command-Address interface) should be in-phase with Input clock with around 100-200ps margin.

 

Is there anything that we do similar to CA training in LPDDR4?

 

Thanks,

- Nirav 

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