03-11-2019 01:01 PM
I receievd this critcal warning during synthesis.should this be resolved within my design. I belived this paramter is gnerated with the ddr3 IP core and not from my design. what is this?
03-12-2019 07:07 AM
The MIG IP (DDR3) is a readonly module therefore I could't make any modification.
I only instantiated it into my design and build on top of it.