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atsuk
Observer
Observer
6,580 Views
Registered: ‎07-25-2014

sys_clk questions

In the first step of the MIG, once I've chosen the QDRII+ option, the first step is for me to select the "Clock Period" (allowable period range 1818-5000ps).

 

1) If I want the FPGA-SRAM interface to operate at 500MHz, is it correct to set this to 2000ps?

 

2) If the memory interface is run from a 250MHz clock (i.e. I'm connecting a 250MHz clock the the sys_clk pins), is it correct to set the "Input Clock Period" to 4000ps (250MHz)?  

 

3) In other words, in the description for the "Input clock Period" it states "Input Clock Period: Select the period for the PLL input clock (CLKIN)."  Is this "PLL input clock (CLKIN)" the same as the clock I connect to the "sys_clk" pins?

 

4) I'm going to connect a 250MHz clock to the sys_clk pin to use as the "system clock for the memory interface".  Is it ok to use this same clock to run the rest of the logic on the FPGA?

 

Thank you for your help.

 

 

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vsrunga
Xilinx Employee
Xilinx Employee
6,569 Views
Registered: ‎07-11-2011

Hi,

 

Your ps calculations are correct.

 

You have not specified your device.

Fabric clock depends on nCK_PER_CLK setting in MIG GUI which is 1/2 or 1/4 of memory operating frequency.

Please refer UG406 for V6 and UG586 for 7 series for more detailed info

 

http://www.xilinx.com/support/documentation/ip_documentation/mig/v3_92/ug406.pdf.

 

http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_3/ug586_7Series_MIS.pdf

 

 

Hope this helps

 

-Vanitha

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yenigal
Xilinx Employee
Xilinx Employee
6,567 Views
Registered: ‎02-06-2013

Hi

 

Please find the answers

 

1) If I want the FPGA-SRAM interface to operate at 500MHz, is it correct to set this to 2000ps?

 

Ans:Yes

 

2) If the memory interface is run from a 250MHz clock (i.e. I'm connecting a 250MHz clock the the sys_clk pins), is it correct to set the "Input Clock Period" to 4000ps (250MHz)?  

 

Ans:Yes(The frequencies which are only possible for your memory frequency and meets the PLL guidelines are shown in the GUI dropdown menu and you can select any one of them as per your requirement,in this case 250Mz can easily generate the memory clk and other clocks and you can select this)

 

3) In other words, in the description for the "Input clock Period" it states "Input Clock Period: Select the period for the PLL input clock (CLKIN)."  Is this "PLL input clock (CLKIN)" the same as the clock I connect to the "sys_clk" pins?

Ans:yes

 

4) I'm going to connect a 250MHz clock to the sys_clk pin to use as the "system clock for the memory interface".  Is it ok to use this same clock to run the rest of the logic on the FPGA?

Ans:Yes you can use this via no buffer option to both logic and MIG or you can modify the PLL to generate an extra clock of 250Mhz and use it as the logic clock.

Regards,

Satish

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