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Observer duke4055
Observer
305 Views
Registered: ‎01-31-2018

ultrascale+ ddr4 mig axi interface

I have some questions about mig ddr4.

1. For setting ddr4 mig with axi interface, if i write & read data with burst length 64(decimal), do i have to set awaddr & araddr increment value (start address : 32'd0) as below?

wire wr_burst_len = 8'd64 ;

always@(posedge clk)

out_axi_awaddr <= out_axi_awaddr + {18'b0,wr_burst_len,6'b0};

 

2. Relationship between axi_address & mig's phy address.

I am using ddr4 sdram(1GB), MT40A512M16HA-083E(Width of addresses - BG(1), Bank(2), ROW(16), Colomn(10))

and c0_ddr4_s_axi_araddr[29:0], c0_ddr4_s_axi_awaddr[29:0]

Memory Address Map : BANK ROW COLUMN

 

Then, c0_ddr4_s_axi_awaddr[9:0] - Column Address

        c0_ddr4_s_axi_awaddr[25:10] - Row Address

        c0_ddr4_s_axi_awaddr[27:26] - Bank Address

        c0_ddr4_s_axi_awaddr[28] - Bank Group Address

        c0_ddr4_s_axi_awaddr[29] - Rank Address

Is that right?

 

3. I want to Write & Read 128-bit counter data with burst length 64.

 then, 

c0_ddr4_s_axi_awlen = 'd63;

c0_ddr4_s_axi_awburst = 'd1;

c0_ddr4_s_axi_awsize =  'd4;

c0_ddr4_s_axi_awburst = 'd1;

axi_read_part same as axi_aw signals.

 

Is that right??

 

Plz help me. 

Thanks.

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Xilinx Employee
Xilinx Employee
199 Views
Registered: ‎01-09-2019

Re: ultrascale+ ddr4 mig axi interface

@duke4055 

Regarding your address bits corresponding to the DDR phy addresses, that looks correct.

With your AXI questions I would look at the ARM protocol specification which can be found here: https://developer.arm.com/docs/ihi0022/d

The main takeaway is that *_awburst is the burst type which when set to 0x1 is INCR, or incrementing.  This means that your AXI transaction should write through the full burst length incrementally (in bytes) and then end your address.  To change addresses passed that point you would likely want to change address by the least significant bits so the code would be more like:

out_axi_awaddr <= out_axi_awaddr + wr_burst_len;

Currently you have it set that the 7th-15th bits would be incremented after each clock edge.

I would also note if you wanted 128-bit data transferred on each beat of your burst, you would need a larger *_awsize to match (that would be 16 instead of 4 bytes).

Thanks,
Caleb
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