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nnjec
Visitor
Visitor
460 Views
Registered: ‎01-08-2020

update Xilinx PHY-ONLY DDR4 IPs MR/RCW setting and run memory Initialization and Calibration

Design Information:- 
 - FPGA Part - XCZU7EV-3FFVC1156 
 - Design is consists of the DDR4 MIG PHY-ONLY IP with the custom memory controller.
 - for DDR4 PHY IP save - restore options are enabled while customizing via Wizard.
 
Design Challenge:- 
  - Design requirement is to update Xilinx PHYs MR/RCW setting and run memory Initialization and Calibration.  
 
Question:- 
here the way by which we are trying to achieve that,
- modifying Xilinx-PHY code and patch out MR0, MR1, MR2 .. MR6 as I/O instead of parameter which is used by init FSM in Xilinx PHY.
- Proposed Procedure:- 
   - keep phy in reset
   - Drive Updated values on patched I/Os
   - Remove reset
   - Assert XSDB restore
   - Drive XSDB interface to update sampled values 
   - Assert Restore done
 
by this we are expecting that Phy should used updated values for initialization and calibration, Is there another way to achieve this or we need to modify steps in our procedure to achieve this ?
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4 Replies
rpr
Moderator
Moderator
413 Views
Registered: ‎11-09-2017

Hi @nnjec 

I believe you are looking MIG Save Restore feature, Refer to save restore on page 68 below link.
https://www.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf

The calibration data is saved in nonvolatile memory when using save restore.
- Issue a save request: Calibration data save in nonvolatile memory

- Issue restore request: Calibration data back to memory controller from the nonvolatile memory.

rpr_0-1623765326173.png

 

Regards
Pratap

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nnjec
Visitor
Visitor
347 Views
Registered: ‎01-08-2020

Hi @rpr

Thanks for the reply.

 

issue SAVE and Restore Request is valid once first time initialization and Calibration is done,right.

but here we want to update MR/RCW setting and use it in First-time initialization and Calibration sequence itself so that's what the previous question is referring to. 

Design Challenge:- 
  - Design requirement is to update Xilinx PHYs MR/RCW setting and run memory Initialization and Calibration.  
 
Question:- 
here the way by which we are trying to achieve that,
- modifying Xilinx-PHY code and patch out MR0, MR1, MR2 .. MR6 as I/O instead of parameter which is used by init FSM in Xilinx PHY.
- Proposed Procedure:- 
   - keep phy in reset
   - Drive Updated values on patched I/Os
   - Remove reset
   - Assert XSDB restore
   - Drive XSDB interface to update sampled values 
   - Assert Restore done
 
by this we are expecting that Phy should used updated values for initialization and calibration, Is there another way to achieve this or we need to modify steps in our procedure to achieve this ?

 

Thanks,

Nirav 

 

 

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kshimizu
Xilinx Employee
Xilinx Employee
277 Views
Registered: ‎03-04-2018

Hello @nnjec ,

 

We recommend using the Xilinx IP without any modification.  So, one of ways are what you mention, and also the save/restore, I suppose.

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

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nnjec
Visitor
Visitor
259 Views
Registered: ‎01-08-2020

Hi @kshimizu,

 

so kshimizu, can we use save/restore although if first-time full initialization and calibration are not completed?

 

Thanks,

-Nirav 

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