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Visitor
Visitor
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Registered: ‎09-03-2009

where are MIG back-to-back read/write details for DDR ?!

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The UG086 v3.1 (MIG User Guide) points out in multiple places that for Spartan-3 DDR/DDR2 implementations,

"Back-to-back write/read operations are supported only within the same bank and row."

(e.g. see page 333, last sentence in item 7 above the section on "Read")

 

I need to use this feature in order to wring maximum bandwidth of the memory.

However, there are missing details with how to do this, especially because of how one is

apparently required to issue the next command *after* signal user_cmd_ack is deasserted (a "long" delay).

 

So one is left wondering, is it OK to violate that requirement if performing a back-to-back to the same bank and row?

(only the Virtex-4 RLDRAM implementation adequately explains how to do back-to-back, but the I/F is different) 

If so, then one still needs to see a timing diagram covering that case.

 

It would be nice to know for sure instead of spending time actually simulating and trying to confirm if it works or not.

Hopefully someone knows this, but I intend to contact Xilinx if there are no replies "soon".

Thanx in advance if you know something about this ... 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-23-2007

Re: where are MIG back-to-back read/write details for DDR ?!

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Take a look at figure 7-11 on page 302 of http://www.xilinx.com/support/documentation/ip_documentation/ug086.pdf.  That shows a sample of 2 back to back reads.  You can issue more reads as needed within the same row in this fashion.  Then set the burst_done appropriately.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-23-2007

Re: where are MIG back-to-back read/write details for DDR ?!

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Take a look at figure 7-11 on page 302 of http://www.xilinx.com/support/documentation/ip_documentation/ug086.pdf.  That shows a sample of 2 back to back reads.  You can issue more reads as needed within the same row in this fashion.  Then set the burst_done appropriately.

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Visitor
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Registered: ‎09-03-2009

Re: where are MIG back-to-back read/write details for DDR ?!

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I suppose I could've slowed down a bit to look more closely at the diagrams, eh? 

Thanx for the fast response!

 

 

 

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