The MMCM_LOCKED signal inside the MIG comes from the MMCM in the DDR4 Infrastructure block and is connected to the DDR4 mem_intfc module. These are below the top level wrapper of the IP.
Now for your specific question the PS block resets come in from the external PS_SRST_B and PS_POR_B pins. In your design you'll have to figure out a way that keeps the PS in reset while the bitstream is loaded on the FPGA and keeps it in reset until the MIG mmcm_locked asserts, and that would have to be routed out on a pin in the PL I/O banks, then routed on hardware to the PS reset input pins. Overall I don't recommend this approach.