cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
sraza
Explorer
Explorer
7,554 Views
Registered: ‎03-13-2012

why is app_rdy getting LOW when I am trying to give data

Jump to solution

Hi all,

 

 

why is app_rdy getting LOW when I am trying to give data, this causes system to work slow. I am watching my data flow over chipscope and this causes problem not only slowing (which is not very much of importanct) but I intermittently found few glitches in my design which I tried to solve but cannot catch whats wrong...hence if there is any way app_rdy can be made HIGH contantly like if you app_wdf_rdy   it is constantly HIGH. (please see the image)

 

Also since I have only implemented only 1 part i.e. write logic by now. I want to confirm that since I am checking over real hardware using Chipscope and DDR3 with FPGA, can I be sure that my data is going back to real DDR3...I want to be sure before I start teh logic for read transmission, please do comment on this issue

 

sample_x.JPG

Tags (2)
0 Kudos
1 Solution

Accepted Solutions
vsrunga
Xilinx Employee
Xilinx Employee
11,021 Views
Registered: ‎07-11-2011

Also since I have only implemented only 1 part i.e. write logic by now. I want to confirm that since I am checking over real hardware using Chipscope and DDR3 with FPGA, can I be sure that my data is going back to real DDR3...I want to be sure before I start teh logic for read transmission

 

>> I believe we  shouldn't take it granted that data was written properyly to DDR unless you read it successfully.

I would suggest you to simulate your traffic and then go for hardware testing.

I believe user guide gives write, read timing waveforms which you can compare against yours.

Alternatively you can also run example deisgn simulation and analuze the waveforms.

 

Hope this helps,

 

Vanitha.

 

 

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post

0 Kudos
4 Replies
vsrunga
Xilinx Employee
Xilinx Employee
7,550 Views
Registered: ‎07-11-2011

Hi,

 

Can you please go through below post, hope it helps.

 

http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/MIG-7-series-Gap-in-continuous-write-read/td-p/365643

 

 

Regards,

Vanitha.

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
sraza
Explorer
Explorer
7,541 Views
Registered: ‎03-13-2012

hi

 

can you also comment on the secon point on my  post?

 

thanks

0 Kudos
vsrunga
Xilinx Employee
Xilinx Employee
11,022 Views
Registered: ‎07-11-2011

Also since I have only implemented only 1 part i.e. write logic by now. I want to confirm that since I am checking over real hardware using Chipscope and DDR3 with FPGA, can I be sure that my data is going back to real DDR3...I want to be sure before I start teh logic for read transmission

 

>> I believe we  shouldn't take it granted that data was written properyly to DDR unless you read it successfully.

I would suggest you to simulate your traffic and then go for hardware testing.

I believe user guide gives write, read timing waveforms which you can compare against yours.

Alternatively you can also run example deisgn simulation and analuze the waveforms.

 

Hope this helps,

 

Vanitha.

 

 

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post

0 Kudos
wangningqin
Visitor
Visitor
7,036 Views
Registered: ‎03-02-2014
have you resolved this question ? i have also have this question ,thank you .....
0 Kudos