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Observer zwl6600233
Observer
417 Views
Registered: ‎10-30-2018

why the MPSoC XCZU2CG SFVA625 didn't support 64bit DDR in PS

I found that the XCZU2CGSFVA625 has 72 PS_DDR_DQ ports,

why it DDR can't to be set to 64bit width

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2 Replies
Moderator
Moderator
377 Views
Registered: ‎11-28-2016

Re: why the MPSoC XCZU2CG SFVA625 didn't support 64bit DDR in PS

Hello @zwl6600233,

I'm looking at the ASCII Pinout File for the XCZU2CG-SFVA625 linked here:
https://www.xilinx.com/support/packagefiles/zuppackages/xczu2cgsfva625pkg.txt

Inside I can see DQ0-DQ31 plus the ECC byte mapped to DQ64-DQ71.
There are no DQ bits between DQ32-DQ63.  This means you can only configure the PS for 32-bit data buses.
32_bit_plus_ecc_bus.PNG

Tags (3)
Moderator
Moderator
289 Views
Registered: ‎11-28-2016

Re: why the MPSoC XCZU2CG SFVA625 didn't support 64bit DDR in PS

Hello @zwl6600233,

I just wanted to follow up and let you know that I created some change requests against UG1075, DS925, and XTP427 to indicate that SBVA484 and SFVA625 Zynq UltraScale+ packages only bring out 32-bits of data + the ECC byte in the PS DDR controller.