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Registered: ‎01-29-2020

zynq mpsoc PS ddr4 calibration fails

We have designed a custom board with zynq ultrascale mpsoc which have a MT40A256M16GE-083E DDR4 memory chip.

The PHY bring up initialization phase in PSU-init tcl hangs after some debugging, we found that the value of PSGR0 is 0x0A instead of 0x0F which means the digital delay line calibration is failed. We also checked voltages of memory parts and all of them are good.

Can you give us any debugging recommendations? 

Does digital line calibration phase need any response from memory parts? or its a zynq internal problem?


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2 Replies
Registered: ‎07-09-2009

Re: zynq mpsoc PS ddr4 calibration fails

First up, is this one of many boards that fail, or all boards, or one of one ? sort out if its an assembly / design problem or not.

Have look if that's a "recommended" part, ie. one that's in the MIG setup, If not, then check the configuration numbers you have entered.

If that all looks good, and it looks like a design feature, check have you designed the track delays / track matching / pin swaps correct.

And double check the board has been made correct, with the correct impedance as you specified.
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Registered: ‎06-16-2013

Re: zynq mpsoc PS ddr4 calibration fails

Hi @mohamad.shabadii 


Which topology are you using ? Fly-by topology or T-branch topology or Cramshell topology ?

If you don't know them or don't consider them, it's route cause.

You must consider proper topology.


Best regards,

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