02-08-2020 09:30 AM
We have designed a custom board with zynq ultrascale mpsoc which have a MT40A256M16GE-083E DDR4 memory chip.
The PHY bring up initialization phase in PSU-init tcl hangs after some debugging, we found that the value of PSGR0 is 0x0A instead of 0x0F which means the digital delay line calibration is failed. We also checked voltages of memory parts and all of them are good.
Can you give us any debugging recommendations?
Does digital line calibration phase need any response from memory parts? or its a zynq internal problem?
02-08-2020 11:21 AM
02-08-2020 12:20 PM
Which topology are you using ? Fly-by topology or T-branch topology or Cramshell topology ?
If you don't know them or don't consider them, it's route cause.
You must consider proper topology.