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Adventurer
Adventurer
187 Views
Registered: ‎10-26-2017

32-bit DDR4 SDRAM MIG with ECC

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Hello,

I am trying to set up a DDR4 interface for the xczu28dr RFSoC. There is no problem setting up the 32-bit MIG interface, but I would like to include 8-bit ECC (40-bit bus total) and the only options the MIG lets me choose are 8, 16, 32, 64, 72. ECC is only available for 72-bit interfaces and I cannot manually check the box. What is the recommended way to do this?

Thanks

Dan

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1 Solution

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Moderator
Moderator
179 Views
Registered: ‎11-28-2016

Re: 32-bit DDR4 SDRAM MIG with ECC

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Hello @dancurry ,

The soft PL DDR4 controller that goes in to the fabric of the FPGA only supports ECC with a 72-bit memory bus where 64-bits are the data payload and 8-bits are the ECC payload.  There is no option for a 32-bit data + 8-bit ECC in the soft PL controller and there are no plans to develop this feature. 

The hardened Processor Subsystem DDR4 controller in the Zynq does allow you to use a 32-bit data + 8-bit ECC option but I'm guessing you're using that memory interface for something else in the design. 

Your other options at this point are to try and hack together a solution from the existing PL DDR4 controller output products to make a custom solution with a 32-bit data payload, or try to use an in-line ECC engine in the data payload so the ECC is calculated outside of the IP and then written in to the controller as part of the AXI data bus and then checked when the data is read.  There may be a 3rd party IP vendor that could provide this solution:
https://www.xilinx.com/alliance.html

Sorry I couldn't be more help on this one.
Thanks,
Ryan.

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1 Reply
Moderator
Moderator
180 Views
Registered: ‎11-28-2016

Re: 32-bit DDR4 SDRAM MIG with ECC

Jump to solution

Hello @dancurry ,

The soft PL DDR4 controller that goes in to the fabric of the FPGA only supports ECC with a 72-bit memory bus where 64-bits are the data payload and 8-bits are the ECC payload.  There is no option for a 32-bit data + 8-bit ECC in the soft PL controller and there are no plans to develop this feature. 

The hardened Processor Subsystem DDR4 controller in the Zynq does allow you to use a 32-bit data + 8-bit ECC option but I'm guessing you're using that memory interface for something else in the design. 

Your other options at this point are to try and hack together a solution from the existing PL DDR4 controller output products to make a custom solution with a 32-bit data payload, or try to use an in-line ECC engine in the data payload so the ECC is calculated outside of the IP and then written in to the controller as part of the AXI data bus and then checked when the data is read.  There may be a 3rd party IP vendor that could provide this solution:
https://www.xilinx.com/alliance.html

Sorry I couldn't be more help on this one.
Thanks,
Ryan.

0 Kudos