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Explorer
Explorer
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Registered: ‎01-23-2018

[AXI DDR]

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Hi,

 

 

I'm implementing a ddr4 controller for a VUP9 FPGA and I wanted to know how should I choose the parameters for this implementation. I have implemented the controller logic but I need to set the AXI and DDR4 parameters in the vivado IP Catalog.

Can you give me some advices about how to choose a correct value?

 

As I understand I have to choose the Configuration and Memory Part depending on the DDR4 that I buy. I want to do transactions of 512 bits to read/write memory.

 

For the CAS latency and data width should can I choose any value? In this case I can choose a data width of 64 bits allowing me to do 8 bursts to do a total of 512 bits? Or it works in another way and each ddr has to have it's own configuration?

 

 Also, one doubt about strobe. If I have 128 bits on the AXI wdata but the DDR width is set to 16 (so i'm doing 8 bursts), wstrobe has to be set to 1 only in this 16 bits or I can set the entire wstrobe as 1 and AXI will take the good data iterating in every burst?

 

Thanks-

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Moderator
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Registered: ‎11-28-2016

Re: [AXI DDR]

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Hello @joel.sanchez,

 

If you want the transactions to be 512-bit then you'll need a 64-bit memory interface since the controller always does a burst length of 8 to the memory.  64-bits x 8 bursts = 512-bits.  The CAS latency is determined by your interface operating rate and the memory device you select.  The entire memory interface (like 8 placements of x8 devices or a 64-bit DIMM) is handled in one configuration.  Ideally I would select the Data Width in the AXI Options tab to match your memory burst size, so in this case it would be 512-bits.  The enumeration of the write strobes and all the other AXI signals are generated automatically based on the configuration in the AXI Options page. AXI protocol dictates that wstrb is always 1 for every 8-bits of data width, so with a 512-bit data width you'll have 64 strobes.

 

In your example for 128-bits on the AXI interface with a 16-bit memory interface the wstrb count will be 16.  The AXI shim to the memory controller handles accepting the single 128-bit AXI write and translates it to the write command of 8 burst of 16-bits.

 

 

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Moderator
Moderator
893 Views
Registered: ‎11-28-2016

Re: [AXI DDR]

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Hello @joel.sanchez,

 

If you want the transactions to be 512-bit then you'll need a 64-bit memory interface since the controller always does a burst length of 8 to the memory.  64-bits x 8 bursts = 512-bits.  The CAS latency is determined by your interface operating rate and the memory device you select.  The entire memory interface (like 8 placements of x8 devices or a 64-bit DIMM) is handled in one configuration.  Ideally I would select the Data Width in the AXI Options tab to match your memory burst size, so in this case it would be 512-bits.  The enumeration of the write strobes and all the other AXI signals are generated automatically based on the configuration in the AXI Options page. AXI protocol dictates that wstrb is always 1 for every 8-bits of data width, so with a 512-bit data width you'll have 64 strobes.

 

In your example for 128-bits on the AXI interface with a 16-bit memory interface the wstrb count will be 16.  The AXI shim to the memory controller handles accepting the single 128-bit AXI write and translates it to the write command of 8 burst of 16-bits.