We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!


AXI4lite and Instruction Cache

Posts: 1
Registered: ‎09-25-2013

AXI4lite and Instruction Cache

Hello everyone,


I have designed an AXI4LITE SDRAM controller, and i work on a spartan6 FPGA. I plan to store  my Microblaze application on SDRAM, and execute it from SDRAM. To make this possible, i have seen in some example projects that instruction cache have to be enabled. My controller is not capable of burst read/write since it is connected to MB through AXI4LITE. When enabling instruction caches, there is a setting called Line length, and it can be set to either 4 or 8, and it means 4 or 8 word access. Is it not possible to use instruction caches to access an external memory using AXI4LITE?