UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
447 Views
Registered: ‎01-26-2017

Accessing MicroBlaze-AXI Slaved DDR4 from PL

Jump to solution

Hi all,

 

I am working on a design that writes data from a MicroBlaze to a slave DDR4 using AXI-DMA. The idea is that the MicroBlaze writes data to the DDR4 which can be read in PL to do some processing stuff. Currently I have the write part working via DMA, but I am not sure how to interface to the DDR4 in PL. I have done designs before where the DDR4 is entirely in PL, which is easy enough to control in FSMs with the MIG user interface. However, as the design uses AXI to map to MicroBlaze and AXI DMA, the design does not allow user interface (i.e must use AXI) Instead I think I am stuck with these signals:

ddr4.PNG

 

I think it might be possible to have an AXI interconnect map to the PL by making its connections external, is this the recommended way of controlling reads to the DDR4 in PL? Is there an application note / guide on how to read the AXI slaved DDR4 from PL side? Thanks for your time

--- Estimated Development time: 2*Pi*(planned completion date) ---
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Adventurer
Adventurer
525 Views
Registered: ‎01-26-2017

Re: Accessing MicroBlaze-AXI Slaved DDR4 from PL

Jump to solution

After doing some reading, I realise that I can have another AXI master connected externally to PL, and use this to drive the DDR4. I believe if the DDR4 is interfacing to a MicroBlaze such as in my design, you are forced into using AXI interface. Actually this turns out to be not too bad, as the AXI specification provides all necessary information for writing a simple FSM for controlling DDR4.

 

Not sure how to handle possible contention between PS master and the PL master but I assume I can just use some kind of semaphore to prevent the PL reading before the PS has written. 

--- Estimated Development time: 2*Pi*(planned completion date) ---
1 Reply
Highlighted
Adventurer
Adventurer
526 Views
Registered: ‎01-26-2017

Re: Accessing MicroBlaze-AXI Slaved DDR4 from PL

Jump to solution

After doing some reading, I realise that I can have another AXI master connected externally to PL, and use this to drive the DDR4. I believe if the DDR4 is interfacing to a MicroBlaze such as in my design, you are forced into using AXI interface. Actually this turns out to be not too bad, as the AXI specification provides all necessary information for writing a simple FSM for controlling DDR4.

 

Not sure how to handle possible contention between PS master and the PL master but I assume I can just use some kind of semaphore to prevent the PL reading before the PS has written. 

--- Estimated Development time: 2*Pi*(planned completion date) ---