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269 Views
Registered: ‎11-27-2017

Alert_n DDR4 in KCU105

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Hi all,

I am reviewing the KCU105 because I am designing a new board based on XCKU040, and also with a 64-bit DDR4 bank. In the UG583, a special point about Alert_n is explained, and it says this pin should be connected to VCCO = 1.2V. However, in the KCU105 schematics, this pin is tied to VTT=0.6V. Why? Is it correct?

 

Thanks,

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Community Manager
Community Manager
211 Views
Registered: ‎07-23-2015

Re: Alert_n DDR4 in KCU105

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ammantas@iaa.es  Always follow UG583 and XTP344 schematic checklist when designing your KU040 boards. The Eval boards are designed well before the chip arrives and so may not be inline with the guidelines of UG583. 

- Giri
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There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
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2 Replies
Community Manager
Community Manager
212 Views
Registered: ‎07-23-2015

Re: Alert_n DDR4 in KCU105

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ammantas@iaa.es  Always follow UG583 and XTP344 schematic checklist when designing your KU040 boards. The Eval boards are designed well before the chip arrives and so may not be inline with the guidelines of UG583. 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------
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Xilinx Employee
Xilinx Employee
203 Views
Registered: ‎08-21-2007

回复: Alert_n DDR4 in KCU105

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The Alert_n is the output pin of DDR4 RDIMM and can be assigned to any general IO of FPGA. 

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