We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!


Block RAM Utilization of Virtual FIFO

Posts: 1
Registered: ‎07-28-2015

Block RAM Utilization of Virtual FIFO



currently I try to connect a vfifo to a DDR2 MIG on a Spartan 6 (xc6slx45t).

I'm wondering why the vfifo needs so much Block RAMs with the configuration below.

After Synthesis: 106 RAMB16

After Mapping: 72 RAMB16


I got these numbers by synthesizing/implementing the example vfifo project.


vfifo parameters:

version: v1.1 (ISE 14.7)

data width: 64 Bits

Burst Size: 512 Bytes

Channels: 2

4KB Pages per channel: 4096

Allocated Space: 32 MByte


Is it correct that so much Block RAMs are used? If yes, why? Or am I doing something wrong?



Posts: 526
Registered: ‎06-10-2008

Re: Block RAM Utilization of Virtual FIFO

I am wondering the same thing. Why does the VFIFO take so many Block RAMs?