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Explorer
Explorer
1,711 Views
Registered: ‎11-28-2011

Bug in MIG Generation 4.0 Vivado 2017.2??

We are currently using a COTS board from Xtreme that has the V7690T. When running the MIG GUI in Vivado 2017.2 IPI  I noticed that the Vccaux_io setting is set to a default value of 2.0V and is grayed out (implying it can't change). Given that the part and Clock Period was the desired one by default (1500ps 666MHz) we can proceed through the GUI, and validate all of the pins. We do get a warning when validating Controller 2 saying that Memory ports are spread across different Vccaux_io regions 3,2.  Ultimately we get to the end of the GUI and click Generate. What is reported in the mig.prj file (see attachment) and consequently in the .xdc file is that Controller 0 is set to 1.8V and NORMAL, and the other 3 controllers are set to 2.0V and are HIGH.  The results in place and route failing DRC

 

ERROR: [DRC VCCAUXIO-3] VCCAUX_IO Group conflicts: VCCAUX_IO Group VCCAUX_IO_G3 (banks: 37, 38, 39) has 66 port(s) with VCCAUX_IO=NORMAL and 41 port(s) with VCCAUX_IO=HIGH. NORMAL and HIGH VCCAUX_IO values cannot both be present in the same VCCAUX_IO group.  

 

It was clear that 2.0V for controller 0 is selected as indicated by the GUI screenshot. I believe this is a bug because if I proceed up to the Pin Selection for Controller 0 screen but DO NO Validate, but back out of the entire project to the first Controller 0 screen it shows 1.8V (see screenshot).

 

So, somehow the voltage setting changes in the background.

 

The other observation is that 1.8V should be the correct option if we are running the memory 666MHz. If the voltage is grayed out how can they be changed?  Well the way to change the voltage is to RE-ENTER the Clock Period "1500" ps into the GUI. The voltage then gets set to the right value. This was done on controllers 1-3 with success. Controller 0 wasn't necessary because remember it automatically changed somehow. This is not apparent to any user. If something is grayed out, it usually implies it can't be changed.

 

Has anyone experienced this?  I suppose most users probably have a different part, and hence are forced to enter new values so they might have experienced this.

Tags (3)
Options for Controller 0.png
Options for Controller 1.png
Options for Controller 0 changed to 1p8V.png
Options for Controller 1 changed to 1p8V.png
mig_prj_ctrlr_0_1.JPG
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9 Replies
Moderator
Moderator
1,685 Views
Registered: ‎02-11-2014

Re: Bug in MIG Generation 4.0 Vivado 2017.2??

Hello @polyee13,

 

It looks like your mig.prj and *.xdc didn't attach to the forum topic. Please retry attaching those for inspection.

 

As for the vccaux value not changing, I do not run into this issue in Vivado 2017.2. If I choose 1500ps, vccaux changes to 1.8V. As soon as I switch to 1249ps and lower (faster frequency) the vccaux value automatically switches to 2.0V.I see this same behavior with every controller I setup in a 4 controller enabled design. The device I am using is a xc7vx690tffg1930-3.

 

Thanks,

Cory

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Explorer
Explorer
1,680 Views
Registered: ‎11-28-2011

Re: Bug in MIG Generation 4.0 Vivado 2017.2??

Cory,

I included a picture of the first couple of sections in the mig.prj file. As you can see it shows Controller 0 having 1.8V and Controller 1 having 2.0V. The .xdc file reflects the same settings so they do match.  I think you mentioned a key word in your response. "If I choose 1500ps, vccaux changes to 1.8V"

 

If you don't modify or re-enter the Clock Period and go through the GUI everything looks like it would default to 2.0V. It isn't until viewing the mig.prj and .xdc that controller 0 is set to 1.8V.

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Moderator
Moderator
1,650 Views
Registered: ‎02-11-2014

Re: Bug in MIG Generation 4.0 Vivado 2017.2??

Hello @polyee13,

 

Which specific FPGA are you using? My default frequency was not 1500ps in the FPGA I chose, so I had to change the frequency to 1500ps to match your flow which then makes the issue not exist.

 

Thanks,

Cory

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Explorer
Explorer
1,647 Views
Registered: ‎11-28-2011

Re: Bug in MIG Generation 4.0 Vivado 2017.2??

We are using the xc7vx690t-ffg1157 speed grade 2

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Explorer
Explorer
1,646 Views
Registered: ‎11-28-2011

Re: Bug in MIG Generation 4.0 Vivado 2017.2??

And the memory is MT41K256M16XX-125

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Moderator
Moderator
1,634 Views
Registered: ‎02-11-2014

Re: Bug in MIG Generation 4.0 Vivado 2017.2??

Hello @polyee13,

 

Using the xc7vx690tffg1157-2 and MT41K256M16XX-125 in Vivado 2018.1, my default frequency is 1250ps (800MHz) and 2.0V for vccaux for Controller 0. When I switch this frequency to 1500ps (666.67MHz) vccaux becomes 1.8V. I then switch to the next controller and the default frequency is again 1250ps with vccaux 2.0V. I do the same as controller 0 and things work as expected.

 

Are you using a custom board file from Xtreme for the COTS board that might be causing the strange behavior you are running into?

 

Thanks,

Cory

 

 

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Explorer
Explorer
1,632 Views
Registered: ‎11-28-2011

Re: Bug in MIG Generation 4.0 Vivado 2017.2??

Cory,

I'm not aware of any custom board file.

 

When I bring up the MIG gui in IPI in Vivado 2017.2 the default frequency is 1500ps and 2.0V for vccaux for Controller 0-3.

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Moderator
Moderator
1,623 Views
Registered: ‎02-11-2014

Re: Bug in MIG Generation 4.0 Vivado 2017.2??

Hello @polyee13,

 

I did not know you were using IP Integrator. I have been using IP Catalog. Let me check this out for you.

 

Thanks,

Cory

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Moderator
Moderator
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Registered: ‎02-11-2014

Re: Bug in MIG Generation 4.0 Vivado 2017.2??

Hello @polyee13,

 

I had no issues in IP Integrator with vccaux being incorrect. The default frequency was again 1250ps (800 MHz) and not 1500ps for each controller.

 

Are you migrating a design to 2017.2 and seeing issues? Is this a fresh design?

 

Thanks,

Cory

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