UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor ted_130706
Visitor
247 Views
Registered: ‎11-07-2018

Can not keep timing of maximum clock skew inside the MIG

Timing of maximum clock skew of RIU_CLK of BITSLICE_CONTROL inside MIG can not be kept

- Vivado : Vivado 2017.4

- FPGA : KintexUltraScale

It is difficult, as it is clock skew.
What could be the cause?

 

The following answers have been checked.

AR# 68169 , 68266

 -- 2017.4 was not covered by TCL.

** First design created in 2016.2

https://www.xilinx.com/support/answers/68266.html

https://www.xilinx.com/support/answers/68169.html

 

AR# 68976

-- Do not use Pblock

https://japan.xilinx.com/support/answers/68976.html

0 Kudos
2 Replies
Moderator
Moderator
103 Views
Registered: ‎11-28-2016

Re: Can not keep timing of maximum clock skew inside the MIG

Hello @ted_130706,

The IP generated default constraints should be able to maintain the correct skews so if you design cannot then it's possible you have a user constraint that broke something in the IP generated default constraint, there's too much congestion in your design, or you have an invalid clocking topology.  I would first check for a user constraint to see if you generated an overly broad set_clock_groups -asynchronous -group [clocks].  Next I would try reducing the amount of logic in your design or try different implementation strategies. Also double check the clock sources in the MIG are correct, meaning a reference clock that's entering in the MIG I/O bank column and that there are no user changes that modify the LOCs for any of the MMCMs or PLLs used by the MIG.

Visitor ted_130706
Visitor
47 Views
Registered: ‎11-07-2018

Re: Can not keep timing of maximum clock skew inside the MIG

Hello ryana ,

Thank you for your reply.

It was strange that skew will occur between BUFG and BITSLICE_CONTROL.(It is a CLK leased line.)

 

I got advice and confirmed the design.

Although the usage rate is not so high, clocks were supplied to other primitives within MIG's IP.

I will try separating the BITSLICE_CONTROL and other primitive clock buffers.

 

 

 

 

0 Kudos