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Visitor sainanxue
Visitor
394 Views
Registered: ‎04-20-2018

Can somebody provide me a VC707 MIG project that can work?

Can somebody share an example of Xilinx black box using VHDL or verilog? I am using System Generator 2015.2, Vivado 2015.2 and Matlab 2014a 64-bit.

 

My issue is explained in more detailed in the following link. I think VHDL code is correct, at least the 3rd one. I want to check an working example to make sure my set up of Xilinx black box has no issues.

https://forums.xilinx.com/t5/Design-Tools-Others/Xilinx-blackbox-data-rate-of-output-port-grew-to-over-1-000/td-p/849935

 

Thanks a lot.

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Xilinx Employee
Xilinx Employee
346 Views
Registered: ‎06-30-2010

Re: Can somebody provide me a VC707 MIG project that can work?

there is a MIG example design for the VC707 given here: https://www.xilinx.com/member/forms/download/design-license.html?cid=389659&filename=xtp206-vc707-mig-c-2015-1.pdf there is a bit file in that folder that can be downloaded directly without having to generate the IP through the steps shown in the tutorial.

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